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* fpga: x300: Update synchronizer constraintWade Fife2021-09-131-1/+1
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* fpga: n3xx: Update synchronizer constraintWade Fife2021-09-131-3/+2
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* fpga: lib: Update example constraint in synchronizerWade Fife2021-09-131-18/+40
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* fpga: Update help message for setupenv.shWade Fife2021-09-101-5/+7
| | | | | Updates the language in setupenv.sh --help to better reflect that there are many locations where Vivado is searched.
* fpga: Remove stale references to UHD_FPGA_DIRWade Fife2021-09-088-16/+8
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* fpga: tools: Add UHD_FPGA_DIR definition to synthesisWade Fife2021-09-083-6/+11
| | | | | | | | | | | | | | | | | This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to the location of the UHD "fpga" directory. This allows you to include files in your out-of-tree modules relative to the FPGA directory. For example, you could include the library header file rfnoc_chdr_utils.vh using the following: `include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" Some simulators may not support `" outside of the context of a `define, in which case you can do the following: `define RFNOC_CHDR_UTILS_PATH \ `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" `include `RFNOC_CHDR_UTILS_PATH
* fpga: Set default part for sim in setupenv.shWade Fife2021-08-306-5/+24
| | | | | | | | | This sets the ARCH and PART_ID environment variables so that the selected part family is used for simulations by default. This can be overridden by changing them in the Makefile for the testbench if a testbench requires a specific part family. Prior to this change, the default was always ARCH=kintex7, PART_ID=xc7k410t/ffg900/-2, which required support for that part to be installed.
* x300: Fix sfpp_io_core tuser widthWade Fife2021-08-271-1/+1
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* fpga: Fix Xilinx bitfile parser for Python 3Martin Braun2021-08-241-31/+54
| | | | | | | | | The script was previously only Python 2 compatible. Python 2 support is now removed, so we don't maintain backwards compatibility with Python 2. This also fixes all linter warnings.
* sim: Update chdr_16sc_to_sc12 testbenchmichael-west2021-08-101-137/+159
| | | | | | | Modified to send 2 packets back to back at each packet size to test output during sequential input packets. Also fixed whitespace. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: Re-order error and data packetsmichael-west2021-08-101-2/+28
| | | | | | | Added delay to error packets so overrun error is back in-band. Avoids dropping good data packets in the case of an overrun. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: Fix sc16 to sc12 convertermichael-west2021-08-101-62/+80
| | | | | | | | | Re-wrote converter to remove clock cycle delay on i_tready when handling residual output and fixed improper handling of tlast during residual data processing. Resolves some USB overflow issues when using sc12 data type on B200 devices. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: rfnoc: Fix EOB loss in DUCWade Fife2021-08-087-218/+1858
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There were some rare corner cases where the EOB could get lost in the DUC due to the dds_timed logic not always passing it through as it should. This resulted in an underflow error message at the end of transmission. This commit also fixes an issue where part of the last packet used a frequency shift of 0 instead of the requested frequency shift, and an issue where the first few samples of a burst used the wrong frequency shift value. Part of the fix includes adding a TUSER port to dds_sin_cos_lut_only. The TUSER port is built into the IP but was disabled. It is now enabled and set to 1 bit wide. This has a very small effect on resource usage and can be left unconnected when not needed. The dds_freq_tune block was shared by the DUC and DDC. To avoid affecting the DDC, a new version, dds_freq_tune_duc, is being added for the DUC to use that has the necessary fixes. The new dds_wrapper.v is a wrapper for the dds_sin_cos_lut_only IP. This IP has the undesirable behavior that new inputs must be provided to push previous outputs through the IP. This wrapper hides that complexity by adding some logic to ensure all data gets pushed through automatically. This logic uses the TUSER port on the IP. Finally, a testbench for dds_timed was added.
* fpga: sim: Add PkgComplex, PkgMath, and PkgRandomWade Fife2021-08-085-0/+546
| | | | | | | | | | | | PkgComplex adds functions for doing complex arithmetic in SystemVerilog simulation. PkgMath provides mathematical operations and constants that aren't built into SystemVerilog, such as a constant for pi and the function round(). PkgRandom adds randomization functions beyond what standard Verilog supports but that don't require any special licenses or simulators.
* fpga: lib: Clean up and document lib filesWade Fife2021-08-083-246/+411
| | | | Clean-up and document axi_tag_time, dds_freq_tune, and axi_sync.
* rfnoc: duc: Remove stale references to CORDICWade Fife2021-08-081-18/+15
| | | | | Updated some comments that still referenced the old CORDIC implementation, which is no longer used.
* N3xx: Fix White Rabbitmichael-west2021-08-041-0/+10
| | | | | | | Reconnect the signals from the White Rabbit module to the TDC in the FPGA. Signed-off-by: michael-west <michael.west@ettus.com>
* fpga: x400: Remove stale information in register mapHumberto Jimenez2021-07-283-9/+9
| | | | | | White Rabbit is not supported in X410, however the register map included an incorrect reference to this unsupported feature. This commit removes the WR reference from both the source and html files.
* fpga: ci: Add testbench pipelineWade Fife2021-07-012-0/+106
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* fpga: x400: Fix x4xx_qsfp_wrapper testbenchWade Fife2021-06-221-0/+3
| | | | | Reorder dependencies so that sc_util_v1_0_vl_rfs.sv gets compiled first when using ModelSim.
* fpga: sim: Check for empty packet in clear_unused_bytesWade Fife2021-06-171-0/+4
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* x400: sim: Move testbenches to sim folderWade Fife2021-06-1713-0/+0
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* fpga: Update testbenches to work in ModelSimWade Fife2021-06-1711-136/+303
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* fpga: x400: Add makefiles for RF testbenchesWade Fife2021-06-177-3/+212
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* fpga: tools: Detect assertions in ModelSim simulationWade Fife2021-06-171-2/+22
| | | | | | | This change allows assertion errors/failures in ModelSim to be detected and causes ModelSim to return a non-zero value when such an assertion error occurs. This allows the return value of ModelSim to be used to determine whether or not the testbench passed.
* fpga: tools: Put SIM_SRCS at end of compile orderWade Fife2021-06-171-1/+1
| | | | | | VHDL depends on the compile order. This commit changes the order so that SIM_SRCS are compiled last with ModelSim to avoid issues with dependencies.
* fpga: tools: Support new FPGA types in viv_simulator.makWade Fife2021-06-171-2/+2
| | | | | | This updates the existing PART_NAME generation used in simulation makefiles to work with newer part families by calling viv_gen_part_id.py to generate the part name needed by Vivado.
* fpga: tools: Fix python2 reference in viv_ip_builder.makWade Fife2021-06-171-1/+1
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* fpga: tools: Add modelsim.excludesWade Fife2021-06-171-0/+18
| | | | | This is a list of testbenches that don't work with ModelSim and should be excluded when running run_testbenches.py.
* fpga: tools: Add modelsim.ini to ModelSim callsWade Fife2021-06-174-7/+38
| | | | | | | | | | | This adds the MSIM_VIV_COMPLIBDIR environment variable to specify a non-default location for the compilation libraries. This also allows a modelsim.ini other than the one in the ModelSim installation folder to be used. By default, the one in the simulation libraries compilation directory will be used. This can be changed by setting MSIM_MODELSIM_INI to the one you want to use, or set it to an empty string to use the one in the ModelSim installation folder.
* fpga: tools: Add features to run_testbenches.pyWade Fife2021-06-171-6/+19
| | | | | | | | | | | | | | | | Run "make ip" in a separate step for each testbench. This allows some testbenches to work better with ModelSim because it needs IP files that aren't known until after the IP is generated. Make run_testbenches.py more log friendly. Add a -l/--logged option for when the output is being logged. In this case, we don't want to display elapsed time every second. Add "Begin TB Log:" and "End TB Log:" to the output to more easily tell where the output from one testbench ends and another begins. Use the basedir argument as the base directory in which to search for testbenches so that a subset of the repo can be easily specified.
* fpga: tools: Add ip target to simulation makefilesWade Fife2021-06-172-2/+6
| | | | | Allow building of just the IP by running "make ip" in simulation directories.
* fpga: tools: Add X410 support for image packagingHumberto Jimenez2021-06-101-0/+24
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* fpga: ci: Add build definitions for FPGA CIWade Fife2021-06-107-0/+483
| | | | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com>
* fpga: x400: zbx: Add support for ZBX CPLDJavier Valenzuela2021-06-1037-0/+17727
| | | | | | | Co-authored-by: Cherwa Vang <cherwa.vang@ni.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com>
* fpga: x400: cpld: Add support for X410 motherboard CPLDMax Köhler2021-06-1042-0/+8377
| | | | | Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
* fpga: x400: Add support for X410 motherboard FPGAWade Fife2021-06-10207-1/+299667
| | | | | | | | | | | | | Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com>
* fpga: sim: Add slave_idle() to PkgAxiStreamBfm.svWade Fife2021-06-101-0/+4
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* fpga: lib: Update register comments in eth_regs.vhWade Fife2021-06-101-1/+5
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* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-1018-5780/+6492
| | | | | | Update rfnoc_image_core.v to take into account the new image_core_name fields and version strings. Add new rfnoc_image_core.vh. Update YAML where needed.
* fpga: Update recommended HDL header guidelineWade Fife2021-06-101-0/+3
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* fpga: tools: Fix part selection in setupenvSam O'Brien2021-06-101-4/+12
| | | | | | | | | | | | | | The script setupenv_base.sh, which is used to setup the development environmnet in the open source toolchain, adds some functions to the shell that are used to interact with vivado. Some of the functions were looking in the wrong argument for the product name. This commit fixes the bug. In addition, supplying an incorrect part name returned a rather opaque error message. This commit also fixes the error handling so that the intended error message is displayed. Signed-off-by: Sam O'Brien <sam.obrien@ni.com>
* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-0810-20/+20
| | | | | Change version from a numeric to a string, in order to differentiate between versions like "1.1" and "1.10".
* fpga: lib: Add modports to SV AXI-Stream blocksWade Fife2021-06-034-8/+8
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* fpga: lib: Add time_increment port to timekeeperWade Fife2021-06-031-17/+43
| | | | | Adds a time_increment port for situations in which the parameter TIME_INCREMENT can't be used. They offer the same behavior.
* fpga: lib: Pipeline ctrlport_timerWade Fife2021-06-031-24/+81
| | | | | | | This pipelines ctrlport_timer to eliminate the long combinational path caused by the time comparisons. This change also removes the PRECISION_BITS parameter and converts it to a signal named time_ignore_bits.
* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-037-13/+28
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* fpga: lib: Add 2 to 1 gearbox moduleWade Fife2021-06-035-0/+517
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* fpga: lib: Add PHASE parameter to sim_clk_genWade Fife2021-06-031-1/+3
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* fpga: lib: Add AXI4 (full) interfaceAndrew Moch2021-06-034-0/+619
| | | | | Add a SystemVerilog interface for connecting AXI4 ports, and an associated header file with helper macros.
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