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| author | michael-west <michael.west@ettus.com> | 2021-08-02 09:29:48 -0700 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-08-04 15:19:58 -0500 |
| commit | c0637bae1e4a0ddb996cf2b7eadfad22f782874b (patch) | |
| tree | 57942ede964a7e455e6d3fb247a64323f81b387e /fpga | |
| parent | ae82759d004fa62c60b7ec36041f7f242e6bf22d (diff) | |
| download | uhd-c0637bae1e4a0ddb996cf2b7eadfad22f782874b.tar.gz uhd-c0637bae1e4a0ddb996cf2b7eadfad22f782874b.tar.bz2 uhd-c0637bae1e4a0ddb996cf2b7eadfad22f782874b.zip | |
N3xx: Fix White Rabbit
Reconnect the signals from the White Rabbit module to the TDC in the
FPGA.
Signed-off-by: michael-west <michael.west@ettus.com>
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp3/top/n3xx/n3xx_mgt_channel_wrapper.v | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/fpga/usrp3/top/n3xx/n3xx_mgt_channel_wrapper.v b/fpga/usrp3/top/n3xx/n3xx_mgt_channel_wrapper.v index 9c9c83922..6fc0470aa 100644 --- a/fpga/usrp3/top/n3xx/n3xx_mgt_channel_wrapper.v +++ b/fpga/usrp3/top/n3xx/n3xx_mgt_channel_wrapper.v @@ -244,6 +244,12 @@ module n3xx_mgt_channel_wrapper #( wire [LANES-1:0] reg_rd_resp_flat; wire [(LANES*REG_DWIDTH)-1:0] reg_rd_data_flat; + wire [LANES-1:0] mod_pps_flat; + wire [LANES-1:0] mod_refclk_flat; + + // NOTE: Connecting WR signals of first lane only + assign mod_pps = mod_pps_flat[0]; + assign mod_refclk = mod_refclk_flat[0]; regport_resp_mux #( .WIDTH (REG_DWIDTH), @@ -338,6 +344,10 @@ module n3xx_mgt_channel_wrapper #( .port_info (port_info[l*32 +: 32]), .device_id (device_id), + // Timebase Outputs + .mod_pps(mod_pps_flat[l]), + .mod_refclk(mod_refclk_flat[l]), + // Sideband White Rabbit Control .wr_reset_n (wr_reset_n), .wr_refclk (wr_refclk), |