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| author | Wade Fife <wade.fife@ettus.com> | 2021-06-10 11:38:47 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-06-17 08:16:59 -0500 |
| commit | b85b796cbc1f897a69ded1f3ecfba8ec92684c11 (patch) | |
| tree | b10bb0281ae375ce64b290942c8e3e4446509576 /fpga | |
| parent | 648c70ae758ab1d15c7ec6cbe57672e8c27640cd (diff) | |
| download | uhd-b85b796cbc1f897a69ded1f3ecfba8ec92684c11.tar.gz uhd-b85b796cbc1f897a69ded1f3ecfba8ec92684c11.tar.bz2 uhd-b85b796cbc1f897a69ded1f3ecfba8ec92684c11.zip | |
fpga: tools: Put SIM_SRCS at end of compile order
VHDL depends on the compile order. This commit changes the order so
that SIM_SRCS are compiled last with ModelSim to avoid issues with
dependencies.
Diffstat (limited to 'fpga')
| -rwxr-xr-x | fpga/usrp3/tools/scripts/launch_vlint.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/tools/scripts/launch_vlint.sh b/fpga/usrp3/tools/scripts/launch_vlint.sh index 43d64c786..c8d9b1d63 100755 --- a/fpga/usrp3/tools/scripts/launch_vlint.sh +++ b/fpga/usrp3/tools/scripts/launch_vlint.sh @@ -78,8 +78,8 @@ VHD_ARGS_FILE=vcomarglist.txt # Replace any directories with the sources they contain SOURCES= SOURCES+=$(replace_dirs_with_source $VLINT_INC_SRCS) -SOURCES+=$(replace_dirs_with_source $VLINT_SIM_SRCS) SOURCES+=$(replace_dirs_with_source $VLINT_DESIGN_SRCS) +SOURCES+=$(replace_dirs_with_source $VLINT_SIM_SRCS) # Separate the files by type and determine include directories to use V_FILES= |