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| author | Wade Fife <wade.fife@ettus.com> | 2021-06-17 15:17:31 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-06-22 16:24:54 -0500 |
| commit | a9395823ed450aefa1c2d0c894dbcf976264365e (patch) | |
| tree | 9940db721e0720d32e3d4e20cda8f474195a4f2c /fpga | |
| parent | 73c999ba4e0753afb445a88520067cb771fdc88e (diff) | |
| download | uhd-a9395823ed450aefa1c2d0c894dbcf976264365e.tar.gz uhd-a9395823ed450aefa1c2d0c894dbcf976264365e.tar.bz2 uhd-a9395823ed450aefa1c2d0c894dbcf976264365e.zip | |
fpga: x400: Fix x4xx_qsfp_wrapper testbench
Reorder dependencies so that sc_util_v1_0_vl_rfs.sv gets compiled
first when using ModelSim.
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp3/top/x400/sim/x4xx_qsfp_wrapper/Makefile | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x400/sim/x4xx_qsfp_wrapper/Makefile b/fpga/usrp3/top/x400/sim/x4xx_qsfp_wrapper/Makefile index b38f30755..cc0033c93 100644 --- a/fpga/usrp3/top/x400/sim/x4xx_qsfp_wrapper/Makefile +++ b/fpga/usrp3/top/x400/sim/x4xx_qsfp_wrapper/Makefile @@ -79,6 +79,8 @@ $(IP_100G_BD_SRCS) \ # ModelSim Specific #------------------------------------------------- +# Note: ipshared/*/hdl/sc_util_*_rfs.sv needs to be compiled before the rest of +# the ipshared files. IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/axi_eth_dma_bd/, \ sim/axi_eth_dma_bd.v \ ip/*/sim/*.h \ @@ -89,6 +91,7 @@ ip/*/bd_0/sim/*.v \ ip/*/bd_0/ip/ip_*/sim/*.v \ ip/*/bd_0/ip/ip_*/sim/*.sv \ ip/*/bd_0/ip/ip_*/sim/*.vhd \ +ipshared/*/hdl/sc_util_*_rfs.sv \ ipshared/*/hdl/*.sv \ ipshared/*/hdl/*.v \ ipshared/*/simulation/*.v \ |