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| author | Wade Fife <wade.fife@ettus.com> | 2021-09-10 15:50:25 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-09-13 13:20:37 -0500 |
| commit | a270c531f07ea3549ec2f3b69a38b2c5298bf47c (patch) | |
| tree | 6278292363ab2e1190818140cc38cb34f4b48c3f /fpga | |
| parent | ab4b0c6e0eacbc68df3f211ce27790b1cfbc002f (diff) | |
| download | uhd-a270c531f07ea3549ec2f3b69a38b2c5298bf47c.tar.gz uhd-a270c531f07ea3549ec2f3b69a38b2c5298bf47c.tar.bz2 uhd-a270c531f07ea3549ec2f3b69a38b2c5298bf47c.zip | |
fpga: x300: Update synchronizer constraint
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp3/top/x300/timing.xdc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/top/x300/timing.xdc b/fpga/usrp3/top/x300/timing.xdc index 1b913456c..ffb868eff 100644 --- a/fpga/usrp3/top/x300/timing.xdc +++ b/fpga/usrp3/top/x300/timing.xdc @@ -596,7 +596,7 @@ set_max_delay -to [get_pins {radio_reset_sync/reset_int*/PRE}] 10.000 #******************************************************************************* ## Asynchronous paths -set_false_path -to [get_pins -hier -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[*]/D}] +set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}] set_false_path -to [get_ports LED_*] set_false_path -to [get_ports {SFPP*_RS0 SFPP*_RS1 SFPP*_SCL SFPP*_SDA SFPP*_TxDisable}] set_false_path -from [get_ports {SFPP*_ModAbs SFPP*_RxLOS SFPP*_SCL SFPP*_SDA SFPP*_TxFault}] |