| Commit message (Expand) | Author | Age | Files | Lines |
* | fpga: ci: Add testbench pipeline | Wade Fife | 2021-07-01 | 2 | -0/+106 |
* | fpga: x400: Fix x4xx_qsfp_wrapper testbench | Wade Fife | 2021-06-22 | 1 | -0/+3 |
* | fpga: sim: Check for empty packet in clear_unused_bytes | Wade Fife | 2021-06-17 | 1 | -0/+4 |
* | x400: sim: Move testbenches to sim folder | Wade Fife | 2021-06-17 | 13 | -0/+0 |
* | fpga: Update testbenches to work in ModelSim | Wade Fife | 2021-06-17 | 11 | -136/+303 |
* | fpga: x400: Add makefiles for RF testbenches | Wade Fife | 2021-06-17 | 7 | -3/+212 |
* | fpga: tools: Detect assertions in ModelSim simulation | Wade Fife | 2021-06-17 | 1 | -2/+22 |
* | fpga: tools: Put SIM_SRCS at end of compile order | Wade Fife | 2021-06-17 | 1 | -1/+1 |
* | fpga: tools: Support new FPGA types in viv_simulator.mak | Wade Fife | 2021-06-17 | 1 | -2/+2 |
* | fpga: tools: Fix python2 reference in viv_ip_builder.mak | Wade Fife | 2021-06-17 | 1 | -1/+1 |
* | fpga: tools: Add modelsim.excludes | Wade Fife | 2021-06-17 | 1 | -0/+18 |
* | fpga: tools: Add modelsim.ini to ModelSim calls | Wade Fife | 2021-06-17 | 4 | -7/+38 |
* | fpga: tools: Add features to run_testbenches.py | Wade Fife | 2021-06-17 | 1 | -6/+19 |
* | fpga: tools: Add ip target to simulation makefiles | Wade Fife | 2021-06-17 | 2 | -2/+6 |
* | fpga: tools: Add X410 support for image packaging | Humberto Jimenez | 2021-06-10 | 1 | -0/+24 |
* | fpga: ci: Add build definitions for FPGA CI | Wade Fife | 2021-06-10 | 7 | -0/+483 |
* | fpga: x400: zbx: Add support for ZBX CPLD | Javier Valenzuela | 2021-06-10 | 37 | -0/+17727 |
* | fpga: x400: cpld: Add support for X410 motherboard CPLD | Max Köhler | 2021-06-10 | 42 | -0/+8377 |
* | fpga: x400: Add support for X410 motherboard FPGA | Wade Fife | 2021-06-10 | 207 | -1/+299667 |
* | fpga: sim: Add slave_idle() to PkgAxiStreamBfm.sv | Wade Fife | 2021-06-10 | 1 | -0/+4 |
* | fpga: lib: Update register comments in eth_regs.vh | Wade Fife | 2021-06-10 | 1 | -1/+5 |
* | fpga: Update rfnoc_image_core for all targets | Wade Fife | 2021-06-10 | 18 | -5780/+6492 |
* | fpga: Update recommended HDL header guideline | Wade Fife | 2021-06-10 | 1 | -0/+3 |
* | fpga: tools: Fix part selection in setupenv | Sam O'Brien | 2021-06-10 | 1 | -4/+12 |
* | fpga: Change RFNoC YAML version numbers to strings | Wade Fife | 2021-06-08 | 10 | -20/+20 |
* | fpga: lib: Add modports to SV AXI-Stream blocks | Wade Fife | 2021-06-03 | 4 | -8/+8 |
* | fpga: lib: Add time_increment port to timekeeper | Wade Fife | 2021-06-03 | 1 | -17/+43 |
* | fpga: lib: Pipeline ctrlport_timer | Wade Fife | 2021-06-03 | 1 | -24/+81 |
* | fpga: lib: Add clock domain comments to interfaces | Wade Fife | 2021-06-03 | 7 | -13/+28 |
* | fpga: lib: Add 2 to 1 gearbox module | Wade Fife | 2021-06-03 | 5 | -0/+517 |
* | fpga: lib: Add PHASE parameter to sim_clk_gen | Wade Fife | 2021-06-03 | 1 | -1/+3 |
* | fpga: lib: Add AXI4 (full) interface | Andrew Moch | 2021-06-03 | 4 | -0/+619 |
* | fpga: lib: add pause support to ethernet xport | Andrew Moch | 2021-06-03 | 6 | -7/+112 |
* | fpga: lib: Add eth_ipv4_internal | Wade Fife | 2021-06-03 | 2 | -0/+442 |
* | fpga: lib: Add zynquplus family to axi_bitq | Humberto Jimenez | 2021-06-03 | 1 | -12/+13 |
* | fpga: tools: Add ability to run commands before route | Wade Fife | 2021-06-03 | 1 | -5/+11 |
* | fpga: tools: Add ability to patch IP during generation | Wade Fife | 2021-06-03 | 2 | -0/+87 |
* | fpga: tools: Add support for RFSoC | Humberto Jimenez | 2021-06-03 | 2 | -9/+9 |
* | fpga: lib: Minor cleanup of axi_lite.vh | Lars Amsel | 2021-06-03 | 1 | -2/+23 |
* | fpga: rfnoc: Add ability to disable output flow control | Wade Fife | 2021-04-14 | 2 | -7/+22 |
* | fpga: lib: Add rx_front_end_gen3 testbench | Wade Fife | 2021-04-09 | 2 | -0/+247 |
* | fpga: lib: Update round_sd to eliminate X from simulation | Wade Fife | 2021-04-09 | 1 | -14/+45 |
* | fpga: lib: Fix simulation of axi_fir_filter | Wade Fife | 2021-04-09 | 1 | -1/+1 |
* | TwinRX: Remove frontend filter | michael-west | 2021-04-08 | 1 | -59/+8 |
* | fpga: docs: Improve documentation of rx_frontend_gen3 | Martin Braun | 2021-04-07 | 1 | -1/+73 |
* | fpga: lib: Fix DDS_SIN_COS_LUT outputs in makefile | Paul Butler | 2021-03-31 | 1 | -1/+1 |
* | fpga: dsp: Fix formatting of rx_dcoffset and add docs | Martin Braun | 2021-03-09 | 1 | -38/+110 |
* | fpga: Remove Python2 support from build system | Martin Braun | 2021-01-04 | 17 | -119/+121 |
* | fpga: e320: Improve timing on LVDS interface | Wade Fife | 2020-12-11 | 4 | -358/+541 |
* | fpga: lib: add glitch free mux module | Max Köhler | 2020-12-03 | 2 | -0/+30 |