fpga: x400: Add support for X410 motherboard FPGA

Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>

12 files changed, 858 insertions, 0 deletions

diff --git a/fpga/usrp3/top/x400/constraints/pins/common.xdc b/fpga/usrp3/top/x400/constraints/pins/common.xdc
new file mode 100644
index 000000000..92b09575b
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/common.xdc
@@ -0,0 +1,192 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   Common pin constraints for X410.
+#
+
+###############################################################################
+# Pin constraints for the MGTs reference clocks
+###############################################################################
+
+set_property PACKAGE_PIN U33 [get_ports {MGT_REFCLK_LMK0_P}]
+set_property PACKAGE_PIN U34 [get_ports {MGT_REFCLK_LMK0_N}]
+
+set_property PACKAGE_PIN T31 [get_ports {MGT_REFCLK_LMK1_P}]
+set_property PACKAGE_PIN T32 [get_ports {MGT_REFCLK_LMK1_N}]
+
+set_property PACKAGE_PIN W33 [get_ports {MGT_REFCLK_LMK2_P}]
+set_property PACKAGE_PIN W34 [get_ports {MGT_REFCLK_LMK2_N}]
+
+set_property PACKAGE_PIN V31 [get_ports {MGT_REFCLK_LMK3_P}]
+set_property PACKAGE_PIN V32 [get_ports {MGT_REFCLK_LMK3_N}]
+
+
+###############################################################################
+# Common pin constraints for the QSFP28 ports
+###############################################################################
+
+set_property PACKAGE_PIN AJ15 [get_ports {QSFP0_MODPRS_n}]
+set_property PACKAGE_PIN AH16 [get_ports {QSFP0_RESET_n}]
+set_property PACKAGE_PIN AH15 [get_ports {QSFP0_LPMODE_n}]
+
+set_property PACKAGE_PIN AL11 [get_ports {QSFP1_MODPRS_n}]
+set_property PACKAGE_PIN AR8  [get_ports {QSFP1_RESET_n}]
+set_property PACKAGE_PIN AT9  [get_ports {QSFP1_LPMODE_n}]
+
+set_property IOSTANDARD LVCMOS12 [get_ports {QSFP*_MODPRS_n QSFP*_RESET_n QSFP*_LPMODE_n}]
+set_property SLEW       SLOW     [get_ports {QSFP*_RESET_n QSFP*_LPMODE_n}]
+
+
+###############################################################################
+# eCPRI future clocks
+###############################################################################
+
+# Input
+set_property PACKAGE_PIN AK17 [get_ports {FPGA_AUX_REF}]
+set_property IOSTANDARD LVCMOS12 [get_ports {FPGA_AUX_REF}]
+
+# Output
+set_property PACKAGE_PIN AG17 [get_ports {FABRIC_CLK_OUT_P}]
+set_property PACKAGE_PIN AH17 [get_ports {FABRIC_CLK_OUT_N}]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports {FABRIC_CLK_OUT_*}]
+
+# GTY_RCV_CLK_P is defined in qsfp_port1
+
+
+###############################################################################
+# Pin constraints for the other PL pins (1.8 V)
+###############################################################################
+
+set_property PACKAGE_PIN F6  [get_ports {DB1_GPIO[0]}]
+set_property PACKAGE_PIN E6  [get_ports {DB1_GPIO[1]}]
+set_property PACKAGE_PIN E9  [get_ports {DB1_GPIO[2]}]
+set_property PACKAGE_PIN E8  [get_ports {DB1_GPIO[3]}]
+set_property PACKAGE_PIN E7  [get_ports {DB1_GPIO[4]}]
+set_property PACKAGE_PIN D6  [get_ports {DB1_GPIO[5]}]
+set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}]
+set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}]
+set_property PACKAGE_PIN C8  [get_ports {DB1_GPIO[8]}]
+set_property PACKAGE_PIN C7  [get_ports {DB1_GPIO[9]}]
+set_property PACKAGE_PIN D9  [get_ports {DB1_GPIO[10]}]
+set_property PACKAGE_PIN D8  [get_ports {DB1_GPIO[11]}]
+set_property PACKAGE_PIN B8  [get_ports {DB1_GPIO[12]}]
+set_property PACKAGE_PIN B7  [get_ports {DB1_GPIO[13]}]
+set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}]
+set_property PACKAGE_PIN B9  [get_ports {DB1_GPIO[15]}]
+set_property PACKAGE_PIN C6  [get_ports {DB1_GPIO[16]}]
+set_property PACKAGE_PIN C5  [get_ports {DB1_GPIO[17]}]
+set_property PACKAGE_PIN B5  [get_ports {DB1_GPIO[18]}]
+set_property PACKAGE_PIN A5  [get_ports {DB1_GPIO[19]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[*]}]
+set_property PULLDOWN   TRUE     [get_ports {DB1_GPIO[*]}]
+set_property IOB        TRUE     [get_ports {DB1_GPIO[*]}]
+
+set_property PACKAGE_PIN A7 [get_ports {DB1_SYNTH_SYNC}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DB1_SYNTH_SYNC}]
+
+set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}]
+set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}]
+set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}]
+set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}]
+set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}]
+set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}]
+set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}]
+set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}]
+set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}]
+set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}]
+set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}]
+set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}]
+set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}]
+set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}]
+set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}]
+set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}]
+set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}]
+set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}]
+set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}]
+set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[*]}]
+set_property PULLDOWN   TRUE     [get_ports {DB0_GPIO[*]}]
+set_property IOB        TRUE     [get_ports {DB0_GPIO[*]}]
+
+set_property PACKAGE_PIN AP5 [get_ports {DB0_SYNTH_SYNC}]
+set_property IOSTANDARD LVCMOS18 [get_ports {DB0_SYNTH_SYNC}]
+
+set_property PACKAGE_PIN A9   [get_ports {LMK_SYNC}]
+set_property IOB         TRUE [get_ports {LMK_SYNC}]
+
+set_property PACKAGE_PIN A10 [get_ports {TRIG_IO}]
+set_property PACKAGE_PIN A6  [get_ports {PPS_IN}]
+set_property PACKAGE_PIN AR7 [get_ports {PL_CPLD_SCLK}]
+set_property PACKAGE_PIN AR6 [get_ports {PL_CPLD_MOSI}]
+set_property PACKAGE_PIN AP6 [get_ports {PL_CPLD_MISO}]
+set_property IOSTANDARD LVCMOS18 [get_ports {LMK_SYNC TRIG_IO PPS_IN PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_MISO}]
+set_property DRIVE      16       [get_ports {PL_CPLD_SCLK}]
+
+
+###############################################################################
+# Pin constraints for the other PL pins (1.2 V)
+###############################################################################
+
+set_property PACKAGE_PIN AL16 [get_ports {PLL_REFCLK_FPGA_P}]
+set_property PACKAGE_PIN AL15 [get_ports {PLL_REFCLK_FPGA_N}]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports {PLL_REFCLK_FPGA_*}]
+
+set_property PACKAGE_PIN G17  [get_ports {BASE_REFCLK_FPGA_P}]
+set_property PACKAGE_PIN F17  [get_ports {BASE_REFCLK_FPGA_N}]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports {BASE_REFCLK_FPGA_*}]
+
+set_property PACKAGE_PIN AF17 [get_ports {SYSREF_FABRIC_P}]
+set_property PACKAGE_PIN AF16 [get_ports {SYSREF_FABRIC_N}]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports {SYSREF_FABRIC_*}]
+
+set_property PACKAGE_PIN J15  [get_ports {DIOA_FPGA[0]}]
+set_property PACKAGE_PIN H15  [get_ports {DIOA_FPGA[1]}]
+set_property PACKAGE_PIN L17  [get_ports {DIOA_FPGA[2]}]
+set_property PACKAGE_PIN K17  [get_ports {DIOA_FPGA[3]}]
+set_property PACKAGE_PIN K16  [get_ports {DIOA_FPGA[4]}]
+set_property PACKAGE_PIN J16  [get_ports {DIOA_FPGA[5]}]
+set_property PACKAGE_PIN K19  [get_ports {DIOA_FPGA[6]}]
+set_property PACKAGE_PIN K18  [get_ports {DIOA_FPGA[7]}]
+set_property PACKAGE_PIN H17  [get_ports {DIOA_FPGA[8]}]
+set_property PACKAGE_PIN H16  [get_ports {DIOA_FPGA[9]}]
+set_property PACKAGE_PIN J19  [get_ports {DIOA_FPGA[10]}]
+set_property PACKAGE_PIN J18  [get_ports {DIOA_FPGA[11]}]
+set_property PACKAGE_PIN M18  [get_ports {DIOB_FPGA[0]}]
+set_property PACKAGE_PIN H18  [get_ports {DIOB_FPGA[1]}]
+set_property PACKAGE_PIN G18  [get_ports {DIOB_FPGA[2]}]
+set_property PACKAGE_PIN G15  [get_ports {DIOB_FPGA[3]}]
+set_property PACKAGE_PIN F15  [get_ports {DIOB_FPGA[4]}]
+set_property PACKAGE_PIN G19  [get_ports {DIOB_FPGA[5]}]
+set_property PACKAGE_PIN F19  [get_ports {DIOB_FPGA[6]}]
+set_property PACKAGE_PIN F16  [get_ports {DIOB_FPGA[7]}]
+set_property PACKAGE_PIN E16  [get_ports {DIOB_FPGA[8]}]
+set_property PACKAGE_PIN E18  [get_ports {DIOB_FPGA[9]}]
+set_property PACKAGE_PIN E17  [get_ports {DIOB_FPGA[10]}]
+set_property PACKAGE_PIN E19  [get_ports {DIOB_FPGA[11]}]
+set_property IOSTANDARD LVCMOS12 [get_ports {DIO*_FPGA[*]}]
+set_property PULLDOWN   true     [get_ports {DIO*_FPGA[*]}]
+
+set_property PACKAGE_PIN AW13 [get_ports {PPS_LED}]
+set_property IOSTANDARD LVCMOS12 [get_ports {PPS_LED}]
+
+set_property PACKAGE_PIN B23  [get_ports {PL_CPLD_JTAGEN}]
+set_property PACKAGE_PIN N21  [get_ports {PL_CPLD_CS0_n}]
+set_property PACKAGE_PIN J24  [get_ports {PL_CPLD_CS1_n}]
+set_property PACKAGE_PIN AN12 [get_ports {CPLD_JTAG_OE_n}]
+set_property IOSTANDARD LVCMOS12 [get_ports {PL_CPLD_JTAGEN PL_CPLD_CS*_n CPLD_JTAG_OE_n}]
+
+
+###############################################################################
+# Unused pins
+###############################################################################
+
+# set_property PACKAGE_PIN D19  [get_ports {PL_CPLD_IRQ}]
+# set_property PACKAGE_PIN AF15 [get_ports {FPGA_TEST}]
+# set_property IOSTANDARD LVCMOS12 [get_ports {FPGA_TEST PL_CPLD_IRQ}]
+
+# set_property PACKAGE_PIN AK16 [get_ports {TDC_SPARE_0}]
+# set_property PACKAGE_PIN AJ16 [get_ports {TDC_SPARE_1}]
+# set_property IOSTANDARD LVCMOS12 [get_ports {TDC_SPARE_*}]
diff --git a/fpga/usrp3/top/x400/constraints/pins/dram.xdc b/fpga/usrp3/top/x400/constraints/pins/dram.xdc
new file mode 100644
index 000000000..d4e412239
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/dram.xdc
@@ -0,0 +1,344 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   DRAM pin constraints for X410.
+#
+
+###############################################################################
+# Pin constraints for DRAM controller 0
+###############################################################################
+
+set_property PACKAGE_PIN AH20 [get_ports DRAM0_ACT_n]
+set_property PACKAGE_PIN AN22 [get_ports {DRAM0_ADDR[0]}]
+set_property PACKAGE_PIN AJ18 [get_ports {DRAM0_ADDR[10]}]
+set_property PACKAGE_PIN AN21 [get_ports {DRAM0_ADDR[11]}]
+set_property PACKAGE_PIN AF20 [get_ports {DRAM0_ADDR[12]}]
+set_property PACKAGE_PIN AJ20 [get_ports {DRAM0_ADDR[13]}]
+set_property PACKAGE_PIN AG18 [get_ports {DRAM0_ADDR[14]}]
+set_property PACKAGE_PIN AK18 [get_ports {DRAM0_ADDR[15]}]
+set_property PACKAGE_PIN AN18 [get_ports {DRAM0_ADDR[16]}]
+set_property PACKAGE_PIN AL20 [get_ports {DRAM0_ADDR[1]}]
+set_property PACKAGE_PIN AK22 [get_ports {DRAM0_ADDR[2]}]
+set_property PACKAGE_PIN AM19 [get_ports {DRAM0_ADDR[3]}]
+set_property PACKAGE_PIN AG20 [get_ports {DRAM0_ADDR[4]}]
+set_property PACKAGE_PIN AT20 [get_ports {DRAM0_ADDR[5]}]
+set_property PACKAGE_PIN AL19 [get_ports {DRAM0_ADDR[6]}]
+set_property PACKAGE_PIN AK21 [get_ports {DRAM0_ADDR[7]}]
+set_property PACKAGE_PIN AL21 [get_ports {DRAM0_ADDR[8]}]
+set_property PACKAGE_PIN AP21 [get_ports {DRAM0_ADDR[9]}]
+set_property PACKAGE_PIN AK19 [get_ports {DRAM0_BA[0]}]
+set_property PACKAGE_PIN AM18 [get_ports {DRAM0_BA[1]}]
+set_property PACKAGE_PIN AJ19 [get_ports {DRAM0_BG[0]}]
+set_property PACKAGE_PIN AL22 [get_ports {DRAM0_CLK_P[0]}]
+set_property PACKAGE_PIN AM22 [get_ports {DRAM0_CLK_N[0]}]
+set_property PACKAGE_PIN AF19 [get_ports {DRAM0_CKE[0]}]
+set_property PACKAGE_PIN AH18 [get_ports {DRAM0_CS_n[0]}]
+set_property PACKAGE_PIN AT17 [get_ports {DRAM0_ODT[0]}]
+set_property PACKAGE_PIN AP15 [get_ports DRAM0_RESET_n]
+set_property PACKAGE_PIN AM20 [get_ports DRAM0_REFCLK_P]
+set_property PACKAGE_PIN AN20 [get_ports DRAM0_REFCLK_N]
+set_property PACKAGE_PIN AR17 [get_ports {DRAM0_DM_n[0]}]
+set_property PACKAGE_PIN AR22 [get_ports {DRAM0_DQS_p[0]}]
+set_property PACKAGE_PIN AT22 [get_ports {DRAM0_DQS_n[0]}]
+set_property PACKAGE_PIN AR18 [get_ports {DRAM0_DQ[0]}]
+set_property PACKAGE_PIN AR19 [get_ports {DRAM0_DQ[1]}]
+set_property PACKAGE_PIN AT19 [get_ports {DRAM0_DQ[2]}]
+set_property PACKAGE_PIN AT21 [get_ports {DRAM0_DQ[3]}]
+set_property PACKAGE_PIN AP18 [get_ports {DRAM0_DQ[4]}]
+set_property PACKAGE_PIN AP19 [get_ports {DRAM0_DQ[5]}]
+set_property PACKAGE_PIN AP20 [get_ports {DRAM0_DQ[6]}]
+set_property PACKAGE_PIN AR21 [get_ports {DRAM0_DQ[7]}]
+set_property PACKAGE_PIN AM12 [get_ports {DRAM0_DM_n[1]}]
+set_property PACKAGE_PIN AM13 [get_ports {DRAM0_DQS_p[1]}]
+set_property PACKAGE_PIN AN13 [get_ports {DRAM0_DQS_n[1]}]
+set_property PACKAGE_PIN AM10 [get_ports {DRAM0_DQ[8]}]
+set_property PACKAGE_PIN AP10 [get_ports {DRAM0_DQ[9]}]
+set_property PACKAGE_PIN AN10 [get_ports {DRAM0_DQ[10]}]
+set_property PACKAGE_PIN AR11 [get_ports {DRAM0_DQ[11]}]
+set_property PACKAGE_PIN AL10 [get_ports {DRAM0_DQ[12]}]
+set_property PACKAGE_PIN AP11 [get_ports {DRAM0_DQ[13]}]
+set_property PACKAGE_PIN AN11 [get_ports {DRAM0_DQ[14]}]
+set_property PACKAGE_PIN AR12 [get_ports {DRAM0_DQ[15]}]
+set_property PACKAGE_PIN AW19 [get_ports {DRAM0_DM_n[2]}]
+set_property PACKAGE_PIN AV21 [get_ports {DRAM0_DQS_p[2]}]
+set_property PACKAGE_PIN AW21 [get_ports {DRAM0_DQS_n[2]}]
+set_property PACKAGE_PIN AV17 [get_ports {DRAM0_DQ[16]}]
+set_property PACKAGE_PIN AV18 [get_ports {DRAM0_DQ[17]}]
+set_property PACKAGE_PIN AU19 [get_ports {DRAM0_DQ[18]}]
+set_property PACKAGE_PIN AU18 [get_ports {DRAM0_DQ[19]}]
+set_property PACKAGE_PIN AU17 [get_ports {DRAM0_DQ[20]}]
+set_property PACKAGE_PIN AW20 [get_ports {DRAM0_DQ[21]}]
+set_property PACKAGE_PIN AU20 [get_ports {DRAM0_DQ[22]}]
+set_property PACKAGE_PIN AV20 [get_ports {DRAM0_DQ[23]}]
+set_property PACKAGE_PIN AV10 [get_ports {DRAM0_DM_n[3]}]
+set_property PACKAGE_PIN AT12 [get_ports {DRAM0_DQS_p[3]}]
+set_property PACKAGE_PIN AT11 [get_ports {DRAM0_DQS_n[3]}]
+set_property PACKAGE_PIN AW9  [get_ports {DRAM0_DQ[24]}]
+set_property PACKAGE_PIN AU12 [get_ports {DRAM0_DQ[25]}]
+set_property PACKAGE_PIN AU10 [get_ports {DRAM0_DQ[26]}]
+set_property PACKAGE_PIN AV12 [get_ports {DRAM0_DQ[27]}]
+set_property PACKAGE_PIN AW8  [get_ports {DRAM0_DQ[28]}]
+set_property PACKAGE_PIN AT10 [get_ports {DRAM0_DQ[29]}]
+set_property PACKAGE_PIN AV11 [get_ports {DRAM0_DQ[30]}]
+set_property PACKAGE_PIN AW11 [get_ports {DRAM0_DQ[31]}]
+set_property PACKAGE_PIN AW14 [get_ports {DRAM0_DM_n[4]}]
+set_property PACKAGE_PIN AV16 [get_ports {DRAM0_DQS_p[4]}]
+set_property PACKAGE_PIN AW16 [get_ports {DRAM0_DQS_n[4]}]
+set_property PACKAGE_PIN AU13 [get_ports {DRAM0_DQ[32]}]
+set_property PACKAGE_PIN AV15 [get_ports {DRAM0_DQ[33]}]
+set_property PACKAGE_PIN AV13 [get_ports {DRAM0_DQ[34]}]
+set_property PACKAGE_PIN AU14 [get_ports {DRAM0_DQ[35]}]
+set_property PACKAGE_PIN AU15 [get_ports {DRAM0_DQ[36]}]
+set_property PACKAGE_PIN AW15 [get_ports {DRAM0_DQ[37]}]
+set_property PACKAGE_PIN AT15 [get_ports {DRAM0_DQ[38]}]
+set_property PACKAGE_PIN AT16 [get_ports {DRAM0_DQ[39]}]
+set_property PACKAGE_PIN AP8  [get_ports {DRAM0_DM_n[5]}]
+set_property PACKAGE_PIN AN8  [get_ports {DRAM0_DQS_p[5]}]
+set_property PACKAGE_PIN AN7  [get_ports {DRAM0_DQS_n[5]}]
+set_property PACKAGE_PIN AM9  [get_ports {DRAM0_DQ[40]}]
+set_property PACKAGE_PIN AR9  [get_ports {DRAM0_DQ[41]}]
+set_property PACKAGE_PIN AL7  [get_ports {DRAM0_DQ[42]}]
+set_property PACKAGE_PIN AM8  [get_ports {DRAM0_DQ[43]}]
+set_property PACKAGE_PIN AL9  [get_ports {DRAM0_DQ[44]}]
+set_property PACKAGE_PIN AP9  [get_ports {DRAM0_DQ[45]}]
+set_property PACKAGE_PIN AL8  [get_ports {DRAM0_DQ[46]}]
+set_property PACKAGE_PIN AM7  [get_ports {DRAM0_DQ[47]}]
+set_property PACKAGE_PIN AK13 [get_ports {DRAM0_DM_n[6]}]
+set_property PACKAGE_PIN AJ14 [get_ports {DRAM0_DQS_p[6]}]
+set_property PACKAGE_PIN AK14 [get_ports {DRAM0_DQS_n[6]}]
+set_property PACKAGE_PIN AH12 [get_ports {DRAM0_DQ[48]}]
+set_property PACKAGE_PIN AJ13 [get_ports {DRAM0_DQ[49]}]
+set_property PACKAGE_PIN AJ12 [get_ports {DRAM0_DQ[50]}]
+set_property PACKAGE_PIN AK12 [get_ports {DRAM0_DQ[51]}]
+set_property PACKAGE_PIN AG12 [get_ports {DRAM0_DQ[52]}]
+set_property PACKAGE_PIN AL14 [get_ports {DRAM0_DQ[53]}]
+set_property PACKAGE_PIN AH13 [get_ports {DRAM0_DQ[54]}]
+set_property PACKAGE_PIN AM14 [get_ports {DRAM0_DQ[55]}]
+set_property PACKAGE_PIN AP13 [get_ports {DRAM0_DM_n[7]}]
+set_property PACKAGE_PIN AN17 [get_ports {DRAM0_DQS_p[7]}]
+set_property PACKAGE_PIN AN16 [get_ports {DRAM0_DQS_n[7]}]
+set_property PACKAGE_PIN AM15 [get_ports {DRAM0_DQ[56]}]
+set_property PACKAGE_PIN AP14 [get_ports {DRAM0_DQ[57]}]
+set_property PACKAGE_PIN AM17 [get_ports {DRAM0_DQ[58]}]
+set_property PACKAGE_PIN AP16 [get_ports {DRAM0_DQ[59]}]
+set_property PACKAGE_PIN AL17 [get_ports {DRAM0_DQ[60]}]
+set_property PACKAGE_PIN AR14 [get_ports {DRAM0_DQ[61]}]
+set_property PACKAGE_PIN AN15 [get_ports {DRAM0_DQ[62]}]
+set_property PACKAGE_PIN AR16 [get_ports {DRAM0_DQ[63]}]
+
+
+set_property IOSTANDARD DIFF_POD12_DCI  [get_ports {DRAM0_DQS_*[*]}]
+set_property IOSTANDARD DIFF_SSTL12     [get_ports {DRAM0_REFCLK_*}]
+set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports {DRAM0_CLK_*[0]}]
+set_property IOSTANDARD LVCMOS12        [get_ports  DRAM0_RESET_n]
+set_property IOSTANDARD POD12_DCI       [get_ports {DRAM0_DM_n[*] \
+                                                    DRAM0_DQ[*]}]
+set_property IOSTANDARD SSTL12_DCI      [get_ports {DRAM0_ACT_n \
+                                                    DRAM0_ADDR[*] \
+                                                    DRAM0_BA[*] \
+                                                    DRAM0_BG[0] \
+                                                    DRAM0_CKE[0] \
+                                                    DRAM0_CS_n[0] \
+                                                    DRAM0_ODT[0]}]
+
+set_property DRIVE      8                [get_ports DRAM0_RESET_n]
+
+set_property SLEW FAST [get_ports {DRAM0_ACT_n \
+                                   DRAM0_ADDR[*] \
+                                   DRAM0_BA[*] \
+                                   DRAM0_BG[0] \
+                                   DRAM0_CLK_*[0] \
+                                   DRAM0_CKE[0] \
+                                   DRAM0_CS_n[0] \
+                                   DRAM0_DM_n[*] \
+                                   DRAM0_DQ[*] \
+                                   DRAM0_DQS_*[*] \
+                                   DRAM0_ODT[0]}]
+
+set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {DRAM0_ACT_n \
+                                                     DRAM0_ADDR[*] \
+                                                     DRAM0_BA[*] \
+                                                     DRAM0_BG[0] \
+                                                     DRAM0_CLK_*[0] \
+                                                     DRAM0_CKE[0] \
+                                                     DRAM0_CS_n[0] \
+                                                     DRAM0_DM_n[*] \
+                                                     DRAM0_DQ[*] \
+                                                     DRAM0_DQS_*[*] \
+                                                     DRAM0_ODT[0]}]
+
+set_property IBUF_LOW_PWR FALSE [get_ports {DRAM0_DM_n[*] \
+                                            DRAM0_DQ[*] \
+                                            DRAM0_DQS_*[*]}]
+
+
+
+###############################################################################
+# Pin constraints for DRAM controller 0
+###############################################################################
+
+set_property PACKAGE_PIN E14 [get_ports DRAM1_ACT_n]
+set_property PACKAGE_PIN B12 [get_ports {DRAM1_ADDR[0]}]
+set_property PACKAGE_PIN G14 [get_ports {DRAM1_ADDR[1]}]
+set_property PACKAGE_PIN D13 [get_ports {DRAM1_ADDR[2]}]
+set_property PACKAGE_PIN F12 [get_ports {DRAM1_ADDR[3]}]
+set_property PACKAGE_PIN C13 [get_ports {DRAM1_ADDR[4]}]
+set_property PACKAGE_PIN D14 [get_ports {DRAM1_ADDR[5]}]
+set_property PACKAGE_PIN C12 [get_ports {DRAM1_ADDR[6]}]
+set_property PACKAGE_PIN C15 [get_ports {DRAM1_ADDR[7]}]
+set_property PACKAGE_PIN H12 [get_ports {DRAM1_ADDR[8]}]
+set_property PACKAGE_PIN H13 [get_ports {DRAM1_ADDR[9]}]
+set_property PACKAGE_PIN A14 [get_ports {DRAM1_ADDR[10]}]
+set_property PACKAGE_PIN K12 [get_ports {DRAM1_ADDR[11]}]
+set_property PACKAGE_PIN D11 [get_ports {DRAM1_ADDR[12]}]
+set_property PACKAGE_PIN J7  [get_ports {DRAM1_ADDR[13]}]
+set_property PACKAGE_PIN A15 [get_ports {DRAM1_ADDR[14]}]
+set_property PACKAGE_PIN B14 [get_ports {DRAM1_ADDR[15]}]
+set_property PACKAGE_PIN E11 [get_ports {DRAM1_ADDR[16]}]
+set_property PACKAGE_PIN A12 [get_ports {DRAM1_BA[0]}]
+set_property PACKAGE_PIN A11 [get_ports {DRAM1_BA[1]}]
+set_property PACKAGE_PIN B13 [get_ports {DRAM1_BG[0]}]
+set_property PACKAGE_PIN E13 [get_ports {DRAM1_CLK_P[0]}]
+set_property PACKAGE_PIN E12 [get_ports {DRAM1_CLK_N[0]}]
+set_property PACKAGE_PIN C11 [get_ports {DRAM1_CKE[0]}]
+set_property PACKAGE_PIN F14 [get_ports {DRAM1_CS_n[0]}]
+set_property PACKAGE_PIN B15 [get_ports {DRAM1_ODT[0]}]
+set_property PACKAGE_PIN G24 [get_ports DRAM1_RESET_n]
+set_property PACKAGE_PIN G13 [get_ports DRAM1_REFCLK_P]
+set_property PACKAGE_PIN G12 [get_ports DRAM1_REFCLK_N]
+set_property PACKAGE_PIN J8  [get_ports {DRAM1_DM_n[0]}]
+set_property PACKAGE_PIN H8  [get_ports {DRAM1_DQS_p[0]}]
+set_property PACKAGE_PIN G8  [get_ports {DRAM1_DQS_n[0]}]
+set_property PACKAGE_PIN G9  [get_ports {DRAM1_DQ[0]}]
+set_property PACKAGE_PIN J9  [get_ports {DRAM1_DQ[1]}]
+set_property PACKAGE_PIN H7  [get_ports {DRAM1_DQ[2]}]
+set_property PACKAGE_PIN H6  [get_ports {DRAM1_DQ[3]}]
+set_property PACKAGE_PIN G7  [get_ports {DRAM1_DQ[4]}]
+set_property PACKAGE_PIN G6  [get_ports {DRAM1_DQ[5]}]
+set_property PACKAGE_PIN F9  [get_ports {DRAM1_DQ[6]}]
+set_property PACKAGE_PIN K9  [get_ports {DRAM1_DQ[7]}]
+set_property PACKAGE_PIN K13 [get_ports {DRAM1_DM_n[1]}]
+set_property PACKAGE_PIN J14 [get_ports {DRAM1_DQS_p[1]}]
+set_property PACKAGE_PIN J13 [get_ports {DRAM1_DQS_n[1]}]
+set_property PACKAGE_PIN F10 [get_ports {DRAM1_DQ[8]}]
+set_property PACKAGE_PIN K10 [get_ports {DRAM1_DQ[9]}]
+set_property PACKAGE_PIN F11 [get_ports {DRAM1_DQ[10]}]
+set_property PACKAGE_PIN H10 [get_ports {DRAM1_DQ[11]}]
+set_property PACKAGE_PIN H11 [get_ports {DRAM1_DQ[12]}]
+set_property PACKAGE_PIN J10 [get_ports {DRAM1_DQ[13]}]
+set_property PACKAGE_PIN J11 [get_ports {DRAM1_DQ[14]}]
+set_property PACKAGE_PIN K11 [get_ports {DRAM1_DQ[15]}]
+set_property PACKAGE_PIN D18 [get_ports {DRAM1_DM_n[2]}]
+set_property PACKAGE_PIN B18 [get_ports {DRAM1_DQS_p[2]}]
+set_property PACKAGE_PIN B17 [get_ports {DRAM1_DQS_n[2]}]
+set_property PACKAGE_PIN A17 [get_ports {DRAM1_DQ[16]}]
+set_property PACKAGE_PIN D15 [get_ports {DRAM1_DQ[17]}]
+set_property PACKAGE_PIN A16 [get_ports {DRAM1_DQ[18]}]
+set_property PACKAGE_PIN D16 [get_ports {DRAM1_DQ[19]}]
+set_property PACKAGE_PIN C17 [get_ports {DRAM1_DQ[20]}]
+set_property PACKAGE_PIN B19 [get_ports {DRAM1_DQ[21]}]
+set_property PACKAGE_PIN A19 [get_ports {DRAM1_DQ[22]}]
+set_property PACKAGE_PIN C16 [get_ports {DRAM1_DQ[23]}]
+set_property PACKAGE_PIN N14 [get_ports {DRAM1_DM_n[3]}]
+set_property PACKAGE_PIN L15 [get_ports {DRAM1_DQS_p[3]}]
+set_property PACKAGE_PIN L14 [get_ports {DRAM1_DQS_n[3]}]
+set_property PACKAGE_PIN N15 [get_ports {DRAM1_DQ[24]}]
+set_property PACKAGE_PIN M12 [get_ports {DRAM1_DQ[25]}]
+set_property PACKAGE_PIN M15 [get_ports {DRAM1_DQ[26]}]
+set_property PACKAGE_PIN M13 [get_ports {DRAM1_DQ[27]}]
+set_property PACKAGE_PIN N17 [get_ports {DRAM1_DQ[28]}]
+set_property PACKAGE_PIN L12 [get_ports {DRAM1_DQ[29]}]
+set_property PACKAGE_PIN M17 [get_ports {DRAM1_DQ[30]}]
+set_property PACKAGE_PIN N13 [get_ports {DRAM1_DQ[31]}]
+set_property PACKAGE_PIN C23 [get_ports {DRAM1_DM_n[4]}]
+set_property PACKAGE_PIN B22 [get_ports {DRAM1_DQS_p[4]}]
+set_property PACKAGE_PIN A22 [get_ports {DRAM1_DQS_n[4]}]
+set_property PACKAGE_PIN B24 [get_ports {DRAM1_DQ[32]}]
+set_property PACKAGE_PIN C21 [get_ports {DRAM1_DQ[33]}]
+set_property PACKAGE_PIN C22 [get_ports {DRAM1_DQ[34]}]
+set_property PACKAGE_PIN A21 [get_ports {DRAM1_DQ[35]}]
+set_property PACKAGE_PIN A24 [get_ports {DRAM1_DQ[36]}]
+set_property PACKAGE_PIN B20 [get_ports {DRAM1_DQ[37]}]
+set_property PACKAGE_PIN C20 [get_ports {DRAM1_DQ[38]}]
+set_property PACKAGE_PIN A20 [get_ports {DRAM1_DQ[39]}]
+set_property PACKAGE_PIN F21 [get_ports {DRAM1_DM_n[5]}]
+set_property PACKAGE_PIN D23 [get_ports {DRAM1_DQS_p[5]}]
+set_property PACKAGE_PIN D24 [get_ports {DRAM1_DQS_n[5]}]
+set_property PACKAGE_PIN E24 [get_ports {DRAM1_DQ[40]}]
+set_property PACKAGE_PIN E22 [get_ports {DRAM1_DQ[41]}]
+set_property PACKAGE_PIN F24 [get_ports {DRAM1_DQ[42]}]
+set_property PACKAGE_PIN E23 [get_ports {DRAM1_DQ[43]}]
+set_property PACKAGE_PIN E21 [get_ports {DRAM1_DQ[44]}]
+set_property PACKAGE_PIN D21 [get_ports {DRAM1_DQ[45]}]
+set_property PACKAGE_PIN F20 [get_ports {DRAM1_DQ[46]}]
+set_property PACKAGE_PIN G20 [get_ports {DRAM1_DQ[47]}]
+set_property PACKAGE_PIN J23 [get_ports {DRAM1_DM_n[6]}]
+set_property PACKAGE_PIN J20 [get_ports {DRAM1_DQS_p[6]}]
+set_property PACKAGE_PIN H20 [get_ports {DRAM1_DQS_n[6]}]
+set_property PACKAGE_PIN L24 [get_ports {DRAM1_DQ[48]}]
+set_property PACKAGE_PIN H23 [get_ports {DRAM1_DQ[49]}]
+set_property PACKAGE_PIN J21 [get_ports {DRAM1_DQ[50]}]
+set_property PACKAGE_PIN H22 [get_ports {DRAM1_DQ[51]}]
+set_property PACKAGE_PIN K24 [get_ports {DRAM1_DQ[52]}]
+set_property PACKAGE_PIN G23 [get_ports {DRAM1_DQ[53]}]
+set_property PACKAGE_PIN H21 [get_ports {DRAM1_DQ[54]}]
+set_property PACKAGE_PIN G22 [get_ports {DRAM1_DQ[55]}]
+set_property PACKAGE_PIN N20 [get_ports {DRAM1_DM_n[7]}]
+set_property PACKAGE_PIN K21 [get_ports {DRAM1_DQS_p[7]}]
+set_property PACKAGE_PIN K22 [get_ports {DRAM1_DQS_n[7]}]
+set_property PACKAGE_PIN M19 [get_ports {DRAM1_DQ[56]}]
+set_property PACKAGE_PIN L21 [get_ports {DRAM1_DQ[57]}]
+set_property PACKAGE_PIN M20 [get_ports {DRAM1_DQ[58]}]
+set_property PACKAGE_PIN L23 [get_ports {DRAM1_DQ[59]}]
+set_property PACKAGE_PIN N19 [get_ports {DRAM1_DQ[60]}]
+set_property PACKAGE_PIN L22 [get_ports {DRAM1_DQ[61]}]
+set_property PACKAGE_PIN L20 [get_ports {DRAM1_DQ[62]}]
+set_property PACKAGE_PIN L19 [get_ports {DRAM1_DQ[63]}]
+
+
+set_property IOSTANDARD DIFF_POD12_DCI  [get_ports {DRAM1_DQS_*[*]}]
+set_property IOSTANDARD DIFF_SSTL12     [get_ports {DRAM1_REFCLK_*}]
+set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports {DRAM1_CLK_*[0]}]
+set_property IOSTANDARD LVCMOS12        [get_ports  DRAM1_RESET_n]
+set_property IOSTANDARD POD12_DCI       [get_ports {DRAM1_DM_n[*] \
+                                                    DRAM1_DQ[*]}]
+set_property IOSTANDARD SSTL12_DCI      [get_ports {DRAM1_ACT_n \
+                                                    DRAM1_ADDR[*] \
+                                                    DRAM1_BA[*] \
+                                                    DRAM1_BG[0] \
+                                                    DRAM1_CKE[0] \
+                                                    DRAM1_CS_n[0] \
+                                                    DRAM1_ODT[0]}]
+
+set_property DRIVE      8                [get_ports DRAM1_RESET_n]
+
+set_property SLEW FAST [get_ports {DRAM1_ACT_n \
+                                   DRAM1_ADDR[*] \
+                                   DRAM1_BA[*] \
+                                   DRAM1_BG[0] \
+                                   DRAM1_CLK_*[0] \
+                                   DRAM1_CKE[0] \
+                                   DRAM1_CS_n[0] \
+                                   DRAM1_DM_n[*] \
+                                   DRAM1_DQ[*] \
+                                   DRAM1_DQS_*[*] \
+                                   DRAM1_ODT[0]}]
+
+set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports {DRAM1_ACT_n \
+                                                     DRAM1_ADDR[*] \
+                                                     DRAM1_BA[*] \
+                                                     DRAM1_BG[0] \
+                                                     DRAM1_CLK_*[0] \
+                                                     DRAM1_CKE[0] \
+                                                     DRAM1_CS_n[0] \
+                                                     DRAM1_DM_n[*] \
+                                                     DRAM1_DQ[*] \
+                                                     DRAM1_DQS_*[*] \
+                                                     DRAM1_ODT[0]}]
+
+set_property IBUF_LOW_PWR FALSE [get_ports {DRAM1_DM_n[*] \
+                                            DRAM1_DQ[*] \
+                                            DRAM1_DQS_*[*]}]
diff --git a/fpga/usrp3/top/x400/constraints/pins/ipass.xdc b/fpga/usrp3/top/x400/constraints/pins/ipass.xdc
new file mode 100644
index 000000000..2c455e1e6
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/ipass.xdc
@@ -0,0 +1,60 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   zHD+iPASS ports (0 and 1) pin constraints for X410.
+#
+
+###############################################################################
+# Pin constraints for the MGTs (zHD+iPASS ports)
+###############################################################################
+
+# Quad 129
+set_property PACKAGE_PIN N38 [get_ports {IPASS1_RX_P[0]}]
+set_property PACKAGE_PIN N39 [get_ports {IPASS1_RX_N[0]}]
+set_property PACKAGE_PIN M36 [get_ports {IPASS1_RX_P[1]}]
+set_property PACKAGE_PIN M37 [get_ports {IPASS1_RX_N[1]}]
+set_property PACKAGE_PIN L38 [get_ports {IPASS1_RX_P[2]}]
+set_property PACKAGE_PIN L39 [get_ports {IPASS1_RX_N[2]}]
+set_property PACKAGE_PIN K36 [get_ports {IPASS1_RX_P[3]}]
+set_property PACKAGE_PIN K37 [get_ports {IPASS1_RX_N[3]}]
+
+set_property PACKAGE_PIN P35 [get_ports {IPASS1_TX_P[0]}]
+set_property PACKAGE_PIN P36 [get_ports {IPASS1_TX_N[0]}]
+set_property PACKAGE_PIN N33 [get_ports {IPASS1_TX_P[1]}]
+set_property PACKAGE_PIN N34 [get_ports {IPASS1_TX_N[1]}]
+set_property PACKAGE_PIN L33 [get_ports {IPASS1_TX_P[2]}]
+set_property PACKAGE_PIN L34 [get_ports {IPASS1_TX_N[2]}]
+set_property PACKAGE_PIN J33 [get_ports {IPASS1_TX_P[3]}]
+set_property PACKAGE_PIN J34 [get_ports {IPASS1_TX_N[3]}]
+
+# Quad 130
+set_property PACKAGE_PIN J38 [get_ports {IPASS0_RX_P[0]}]
+set_property PACKAGE_PIN J39 [get_ports {IPASS0_RX_N[0]}]
+set_property PACKAGE_PIN H36 [get_ports {IPASS0_RX_P[1]}]
+set_property PACKAGE_PIN H37 [get_ports {IPASS0_RX_N[1]}]
+set_property PACKAGE_PIN G38 [get_ports {IPASS0_RX_P[2]}]
+set_property PACKAGE_PIN G39 [get_ports {IPASS0_RX_N[2]}]
+set_property PACKAGE_PIN F36 [get_ports {IPASS0_RX_P[3]}]
+set_property PACKAGE_PIN F37 [get_ports {IPASS0_RX_N[3]}]
+
+set_property PACKAGE_PIN H31 [get_ports {IPASS0_TX_P[0]}]
+set_property PACKAGE_PIN H32 [get_ports {IPASS0_TX_N[0]}]
+set_property PACKAGE_PIN G33 [get_ports {IPASS0_TX_P[1]}]
+set_property PACKAGE_PIN G34 [get_ports {IPASS0_TX_N[1]}]
+set_property PACKAGE_PIN F31 [get_ports {IPASS0_TX_P[2]}]
+set_property PACKAGE_PIN F32 [get_ports {IPASS0_TX_N[2]}]
+set_property PACKAGE_PIN E33 [get_ports {IPASS0_TX_P[3]}]
+set_property PACKAGE_PIN E34 [get_ports {IPASS0_TX_N[3]}]
+
+
+###############################################################################
+# Pin constraints for PCIe-related signals
+###############################################################################
+set_property PACKAGE_PIN F22  [get_ports {IPASS_SIDEBAND[0]}]
+set_property PACKAGE_PIN D20  [get_ports {IPASS_SIDEBAND[1]}]
+set_property PACKAGE_PIN AG14 [get_ports {PCIE_RESET}]
+
+set_property IOSTANDARD  LVCMOS12 [get_ports {IPASS_SIDEBAND[*] PCIE_RESET}]
diff --git a/fpga/usrp3/top/x400/constraints/pins/qsfp0_0.xdc b/fpga/usrp3/top/x400/constraints/pins/qsfp0_0.xdc
new file mode 100644
index 000000000..a285d1b63
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/qsfp0_0.xdc
@@ -0,0 +1,21 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   QSFP28 Port 0 (Lane 0) pin constraints for X410.
+#
+
+###############################################################################
+# Pin constraints for the MGTs (QSFP28 ports)
+###############################################################################
+
+# Bank 131 (Quad X0Y4, Lanes X0Y16-X0Y19)
+# Lane 0 (X0Y16)
+
+set_property PACKAGE_PIN E38  [get_ports {QSFP0_0_RX_P}]
+set_property PACKAGE_PIN E39  [get_ports {QSFP0_0_RX_N}]
+
+set_property PACKAGE_PIN D31  [get_ports {QSFP0_0_TX_P}]
+set_property PACKAGE_PIN D32  [get_ports {QSFP0_0_TX_N}]
diff --git a/fpga/usrp3/top/x400/constraints/pins/qsfp0_1.xdc b/fpga/usrp3/top/x400/constraints/pins/qsfp0_1.xdc
new file mode 100644
index 000000000..38f376f50
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/qsfp0_1.xdc
@@ -0,0 +1,21 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   QSFP28 Port 0 (Lane 1) pin constraints for X410.
+#
+
+###############################################################################
+# Pin constraints for the MGTs (QSFP28 ports)
+###############################################################################
+
+# Bank 131 (Quad X0Y4, Lanes X0Y16-X0Y19)
+# Lane 1 (X0Y17)
+
+set_property PACKAGE_PIN D36  [get_ports {QSFP0_1_RX_P}]
+set_property PACKAGE_PIN D37  [get_ports {QSFP0_1_RX_N}]
+
+set_property PACKAGE_PIN C33  [get_ports {QSFP0_1_TX_P}]
+set_property PACKAGE_PIN C34  [get_ports {QSFP0_1_TX_N}]
diff --git a/fpga/usrp3/top/x400/constraints/pins/qsfp0_2.xdc b/fpga/usrp3/top/x400/constraints/pins/qsfp0_2.xdc
new file mode 100644
index 000000000..8344b4cb6
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/qsfp0_2.xdc
@@ -0,0 +1,21 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   QSFP28 Port 0 (Lane 2) pin constraints for X410.
+#
+
+###############################################################################
+# Pin constraints for the MGTs (QSFP28 ports)
+###############################################################################
+
+# Bank 131 (Quad X0Y4, Lanes X0Y16-X0Y19)
+# Lane 2 (X0Y18)
+
+set_property PACKAGE_PIN C38  [get_ports {QSFP0_2_RX_P}]
+set_property PACKAGE_PIN C39  [get_ports {QSFP0_2_RX_N}]
+
+set_property PACKAGE_PIN B31  [get_ports {QSFP0_2_TX_P}]
+set_property PACKAGE_PIN B32  [get_ports {QSFP0_2_TX_N}]
diff --git a/fpga/usrp3/top/x400/constraints/pins/qsfp0_3.xdc b/fpga/usrp3/top/x400/constraints/pins/qsfp0_3.xdc
new file mode 100644
index 000000000..2d1823988
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/qsfp0_3.xdc
@@ -0,0 +1,21 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   QSFP28 Port 0 (Lane 3) pin constraints for X410.
+#
+
+###############################################################################
+# Pin constraints for the MGTs (QSFP28 ports)
+###############################################################################
+
+# Bank 131 (Quad X0Y4, Lanes X0Y16-X0Y19)
+# Lane 3 (X0Y19)
+
+set_property PACKAGE_PIN B36  [get_ports {QSFP0_3_RX_P}]
+set_property PACKAGE_PIN B37  [get_ports {QSFP0_3_RX_N}]
+
+set_property PACKAGE_PIN A33  [get_ports {QSFP0_3_TX_P}]
+set_property PACKAGE_PIN A34  [get_ports {QSFP0_3_TX_N}]
diff --git a/fpga/usrp3/top/x400/constraints/pins/qsfp1_0.xdc b/fpga/usrp3/top/x400/constraints/pins/qsfp1_0.xdc
new file mode 100644
index 000000000..2c68bf7db
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/qsfp1_0.xdc
@@ -0,0 +1,29 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   QSFP28 Port 1 (Lane 0) pin constraints for X410.
+#
+
+###############################################################################
+# Pin constraints for the MGTs (QSFP28 ports)
+###############################################################################
+
+# Bank 128 (Quad X0Y1, Lanes X0Y4-X0Y7)
+# Lane 0 (X0Y4)
+
+set_property PACKAGE_PIN AA38 [get_ports {QSFP1_0_RX_P}]
+set_property PACKAGE_PIN AA39 [get_ports {QSFP1_0_RX_N}]
+
+set_property PACKAGE_PIN Y35  [get_ports {QSFP1_0_TX_P}]
+set_property PACKAGE_PIN Y36  [get_ports {QSFP1_0_TX_N}]
+
+###############################################################################
+# GTY_RCV_CLK_P can only be used with QSFP1
+###############################################################################
+
+set_property PACKAGE_PIN Y31 [get_ports {GTY_RCV_CLK_P}]
+set_property PACKAGE_PIN Y32 [get_ports {GTY_RCV_CLK_N}]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports {GTY_RCV_CLK_*}]
diff --git a/fpga/usrp3/top/x400/constraints/pins/qsfp1_1.xdc b/fpga/usrp3/top/x400/constraints/pins/qsfp1_1.xdc
new file mode 100644
index 000000000..cd0bb5459
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/qsfp1_1.xdc
@@ -0,0 +1,21 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   QSFP28 Port 1 (Lane 1) pin constraints for X410.
+#
+
+###############################################################################
+# Pin constraints for the MGTs (QSFP28 ports)
+###############################################################################
+
+# Bank 128 (Quad X0Y1, Lanes X0Y4-X0Y7)
+# Lane 1 (X0Y5)
+
+set_property PACKAGE_PIN W38  [get_ports {QSFP1_1_RX_P}]
+set_property PACKAGE_PIN W39  [get_ports {QSFP1_1_RX_N}]
+
+set_property PACKAGE_PIN V35  [get_ports {QSFP1_1_TX_P}]
+set_property PACKAGE_PIN V36  [get_ports {QSFP1_1_TX_N}]
diff --git a/fpga/usrp3/top/x400/constraints/pins/qsfp1_2.xdc b/fpga/usrp3/top/x400/constraints/pins/qsfp1_2.xdc
new file mode 100644
index 000000000..4e267c2c7
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/qsfp1_2.xdc
@@ -0,0 +1,21 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   QSFP28 Port 1 (Lane 2) pin constraints for X410.
+#
+
+###############################################################################
+# Pin constraints for the MGTs (QSFP28 ports)
+###############################################################################
+
+# Bank 128 (Quad X0Y1, Lanes X0Y4-X0Y7)
+# Lane 2 (X0Y6)
+
+set_property PACKAGE_PIN U38  [get_ports {QSFP1_2_RX_P}]
+set_property PACKAGE_PIN U39  [get_ports {QSFP1_2_RX_N}]
+
+set_property PACKAGE_PIN T35  [get_ports {QSFP1_2_TX_P}]
+set_property PACKAGE_PIN T36  [get_ports {QSFP1_2_TX_N}]
diff --git a/fpga/usrp3/top/x400/constraints/pins/qsfp1_3.xdc b/fpga/usrp3/top/x400/constraints/pins/qsfp1_3.xdc
new file mode 100644
index 000000000..e56ee3b7e
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/qsfp1_3.xdc
@@ -0,0 +1,21 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   QSFP28 Port 1 (Lane 3) pin constraints for X410.
+#
+
+###############################################################################
+# Pin constraints for the MGTs (QSFP28 ports)
+###############################################################################
+
+# Bank 128 (Quad X0Y1, Lanes X0Y4-X0Y7)
+# Lane 3 (X0Y7)
+
+set_property PACKAGE_PIN R38  [get_ports {QSFP1_3_RX_P}]
+set_property PACKAGE_PIN R39  [get_ports {QSFP1_3_RX_N}]
+
+set_property PACKAGE_PIN R33  [get_ports {QSFP1_3_TX_P}]
+set_property PACKAGE_PIN R34  [get_ports {QSFP1_3_TX_N}]
diff --git a/fpga/usrp3/top/x400/constraints/pins/rfdc_2x2.xdc b/fpga/usrp3/top/x400/constraints/pins/rfdc_2x2.xdc
new file mode 100644
index 000000000..140150d17
--- /dev/null
+++ b/fpga/usrp3/top/x400/constraints/pins/rfdc_2x2.xdc
@@ -0,0 +1,86 @@
+#
+# Copyright 2021 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#   RF data converters pin constraints for X410.
+#   Note: commented constraints are left for documentation purposes.
+#
+
+# SYSREF input for data converters.
+set_property PACKAGE_PIN U4  [get_ports {SYSREF_RF_N}]
+set_property PACKAGE_PIN U5  [get_ports {SYSREF_RF_P}]
+
+###############################################################################
+# Pin constraints for the ADCs
+###############################################################################
+
+# ADC Reference Clocks for Slot 0 (DBA)
+set_property PACKAGE_PIN AF5 [get_ports {ADC_CLK_P[0]}]
+set_property PACKAGE_PIN AF4 [get_ports {ADC_CLK_N[0]}]
+set_property PACKAGE_PIN AD5 [get_ports {ADC_CLK_P[1]}]
+set_property PACKAGE_PIN AD4 [get_ports {ADC_CLK_N[1]}]
+
+# ADC Reference Clocks for Slot 1 (DBB)
+set_property PACKAGE_PIN AB5 [get_ports {ADC_CLK_P[2]}]
+set_property PACKAGE_PIN AB4 [get_ports {ADC_CLK_N[2]}]
+set_property PACKAGE_PIN Y5  [get_ports {ADC_CLK_P[3]}]
+set_property PACKAGE_PIN Y4  [get_ports {ADC_CLK_N[3]}]
+
+# ADC Inputs for Slot 0 (DBA)
+# Note: numbering here does NOT match schematic, but it is the right order
+# according to RF BD Connection spec.
+# set_property PACKAGE_PIN AH2 [get_ports {DB0_RX_P[3]}]
+# set_property PACKAGE_PIN AH1 [get_ports {DB0_RX_N[3]}]
+# set_property PACKAGE_PIN AK2 [get_ports {DB0_RX_P[2]}]
+# set_property PACKAGE_PIN AK1 [get_ports {DB0_RX_N[2]}]
+set_property PACKAGE_PIN AM2 [get_ports {DB0_RX_P[1]}]
+set_property PACKAGE_PIN AM1 [get_ports {DB0_RX_N[1]}]
+set_property PACKAGE_PIN AP2 [get_ports {DB0_RX_P[0]}]
+set_property PACKAGE_PIN AP1 [get_ports {DB0_RX_N[0]}]
+
+# ADC Inputs for Slot 1 (DBB)
+# Note: numbering here does NOT match schematic, but it is the right order
+# according to RF BD Connection spec.
+# set_property PACKAGE_PIN Y2  [get_ports {DB1_RX_P[3]}]
+# set_property PACKAGE_PIN Y1  [get_ports {DB1_RX_N[3]}]
+# set_property PACKAGE_PIN AB2 [get_ports {DB1_RX_P[2]}]
+# set_property PACKAGE_PIN AB1 [get_ports {DB1_RX_N[2]}]
+set_property PACKAGE_PIN AD2 [get_ports {DB1_RX_P[1]}]
+set_property PACKAGE_PIN AD1 [get_ports {DB1_RX_N[1]}]
+set_property PACKAGE_PIN AF2 [get_ports {DB1_RX_P[0]}]
+set_property PACKAGE_PIN AF1 [get_ports {DB1_RX_N[0]}]
+
+
+###############################################################################
+# Pin constraints for the DACs
+###############################################################################
+
+# DAC Reference Clock for Slot 0 (DBA)
+set_property PACKAGE_PIN R5  [get_ports {DAC_CLK_P[0]}]
+set_property PACKAGE_PIN R4  [get_ports {DAC_CLK_N[0]}]
+
+# DAC Reference Clock for Slot 1 (DBB)
+set_property PACKAGE_PIN N5  [get_ports {DAC_CLK_P[1]}]
+set_property PACKAGE_PIN N4  [get_ports {DAC_CLK_N[1]}]
+
+# DAC Outputs for Slot 0 (DBA)
+set_property PACKAGE_PIN U2  [get_ports {DB0_TX_P[0]}]
+set_property PACKAGE_PIN U1  [get_ports {DB0_TX_N[0]}]
+set_property PACKAGE_PIN R2  [get_ports {DB0_TX_P[1]}]
+set_property PACKAGE_PIN R1  [get_ports {DB0_TX_N[1]}]
+# set_property PACKAGE_PIN N2  [get_ports {DB0_TX_P[2]}]
+# set_property PACKAGE_PIN N1  [get_ports {DB0_TX_N[2]}]
+# set_property PACKAGE_PIN L2  [get_ports {DB0_TX_P[3]}]
+# set_property PACKAGE_PIN L1  [get_ports {DB0_TX_N[3]}]
+
+# DAC Outputs for Slot 1 (DBB)
+set_property PACKAGE_PIN J2  [get_ports {DB1_TX_P[0]}]
+set_property PACKAGE_PIN J1  [get_ports {DB1_TX_N[0]}]
+set_property PACKAGE_PIN G2  [get_ports {DB1_TX_P[1]}]
+set_property PACKAGE_PIN G1  [get_ports {DB1_TX_N[1]}]
+# set_property PACKAGE_PIN E2  [get_ports {DB1_TX_P[2]}]
+# set_property PACKAGE_PIN E1  [get_ports {DB1_TX_N[2]}]
+# set_property PACKAGE_PIN C2  [get_ports {DB1_TX_P[3]}]
+# set_property PACKAGE_PIN C1  [get_ports {DB1_TX_N[3]}]