diff options
Diffstat (limited to 'fpga/usrp3/top/x400/constraints/pins/qsfp0_1.xdc')
| -rw-r--r-- | fpga/usrp3/top/x400/constraints/pins/qsfp0_1.xdc | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x400/constraints/pins/qsfp0_1.xdc b/fpga/usrp3/top/x400/constraints/pins/qsfp0_1.xdc new file mode 100644 index 000000000..38f376f50 --- /dev/null +++ b/fpga/usrp3/top/x400/constraints/pins/qsfp0_1.xdc @@ -0,0 +1,21 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Description: +# QSFP28 Port 0 (Lane 1) pin constraints for X410. +# + +############################################################################### +# Pin constraints for the MGTs (QSFP28 ports) +############################################################################### + +# Bank 131 (Quad X0Y4, Lanes X0Y16-X0Y19) +# Lane 1 (X0Y17) + +set_property PACKAGE_PIN D36 [get_ports {QSFP0_1_RX_P}] +set_property PACKAGE_PIN D37 [get_ports {QSFP0_1_RX_N}] + +set_property PACKAGE_PIN C33 [get_ports {QSFP0_1_TX_P}] +set_property PACKAGE_PIN C34 [get_ports {QSFP0_1_TX_N}] |