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| author | Humberto Jimenez <humberto.jimenez@ni.com> | 2020-05-11 09:10:12 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-05-12 13:47:20 -0500 |
| commit | be252febd001feac093b36c987d276720e4244ab (patch) | |
| tree | eb25fdf474272337d806f973d37d25b612d5d747 /fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl | |
| parent | 246cb52188498484851361355230b29eb3ac018b (diff) | |
| download | uhd-be252febd001feac093b36c987d276720e4244ab.tar.gz uhd-be252febd001feac093b36c987d276720e4244ab.tar.bz2 uhd-be252febd001feac093b36c987d276720e4244ab.zip | |
fpga: tools: Fix HLS IP build with Cygwin
Diffstat (limited to 'fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl')
| -rw-r--r-- | fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl b/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl index f32bfa876..7f4e76b4a 100644 --- a/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl +++ b/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl @@ -8,7 +8,12 @@ set part_name $::env(PART_NAME) ;# Full Xilinx part name set hls_ip_name $::env(HLS_IP_NAME) ;# High level synthesis IP name set hls_ip_srcs $::env(HLS_IP_SRCS) ;# High level synthesis IP source files -set hls_ip_inc $::env(HLS_IP_INCLUDES) ;# High level synthesis IP include directories + +if {[info exists env(HLS_IP_INCLUDES)]} { + set hls_ip_inc $::env(HLS_IP_INCLUDES); # High level synthesis IP include directories +} else { + set hls_ip_inc {} +} # --------------------------------------- # Vivado Commands |