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-rw-r--r--fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl7
1 files changed, 6 insertions, 1 deletions
diff --git a/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl b/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl
index f32bfa876..7f4e76b4a 100644
--- a/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl
+++ b/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl
@@ -8,7 +8,12 @@
set part_name $::env(PART_NAME) ;# Full Xilinx part name
set hls_ip_name $::env(HLS_IP_NAME) ;# High level synthesis IP name
set hls_ip_srcs $::env(HLS_IP_SRCS) ;# High level synthesis IP source files
-set hls_ip_inc $::env(HLS_IP_INCLUDES) ;# High level synthesis IP include directories
+
+if {[info exists env(HLS_IP_INCLUDES)]} {
+ set hls_ip_inc $::env(HLS_IP_INCLUDES); # High level synthesis IP include directories
+} else {
+ set hls_ip_inc {}
+}
# ---------------------------------------
# Vivado Commands