From be252febd001feac093b36c987d276720e4244ab Mon Sep 17 00:00:00 2001 From: Humberto Jimenez Date: Mon, 11 May 2020 09:10:12 -0500 Subject: fpga: tools: Fix HLS IP build with Cygwin --- fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl') diff --git a/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl b/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl index f32bfa876..7f4e76b4a 100644 --- a/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl +++ b/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl @@ -8,7 +8,12 @@ set part_name $::env(PART_NAME) ;# Full Xilinx part name set hls_ip_name $::env(HLS_IP_NAME) ;# High level synthesis IP name set hls_ip_srcs $::env(HLS_IP_SRCS) ;# High level synthesis IP source files -set hls_ip_inc $::env(HLS_IP_INCLUDES) ;# High level synthesis IP include directories + +if {[info exists env(HLS_IP_INCLUDES)]} { + set hls_ip_inc $::env(HLS_IP_INCLUDES); # High level synthesis IP include directories +} else { + set hls_ip_inc {} +} # --------------------------------------- # Vivado Commands -- cgit v1.2.3