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| author | Humberto Jimenez <humberto.jimenez@ni.com> | 2020-05-11 09:10:12 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-05-12 13:47:20 -0500 |
| commit | be252febd001feac093b36c987d276720e4244ab (patch) | |
| tree | eb25fdf474272337d806f973d37d25b612d5d747 /fpga | |
| parent | 246cb52188498484851361355230b29eb3ac018b (diff) | |
| download | uhd-be252febd001feac093b36c987d276720e4244ab.tar.gz uhd-be252febd001feac093b36c987d276720e4244ab.tar.bz2 uhd-be252febd001feac093b36c987d276720e4244ab.zip | |
fpga: tools: Fix HLS IP build with Cygwin
Diffstat (limited to 'fpga')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_hls_ip_builder.mak | 7 | ||||
| -rw-r--r-- | fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl | 7 |
2 files changed, 10 insertions, 4 deletions
diff --git a/fpga/usrp3/tools/make/viv_hls_ip_builder.mak b/fpga/usrp3/tools/make/viv_hls_ip_builder.mak index 67b52ed2a..77f09157f 100644 --- a/fpga/usrp3/tools/make/viv_hls_ip_builder.mak +++ b/fpga/usrp3/tools/make/viv_hls_ip_builder.mak @@ -9,6 +9,7 @@ # $3 = HLS_IP_SRCS (Absolute paths to the HLS IP source files) # $4 = HLS_IP_SRC_DIR (Absolute path to the top level HLS IP src dir) # $5 = HLS_IP_BUILD_DIR (Absolute path to the top level HLS IP build dir) +# $6 = HLS_IP_INCLUDES (Absolute path to IP include dir) # Prereqs: # - TOOLS_DIR must be defined globally # ------------------------------------------------------------------- @@ -19,15 +20,15 @@ BUILD_VIVADO_HLS_IP = \ echo "========================================================"; \ export HLS_IP_NAME=$(1); \ export PART_NAME=$(subst /,,$(2)); \ - export HLS_IP_SRCS='$(3)'; \ - export HLS_IP_INCLUDES='$(6)'; \ + export HLS_IP_SRCS=$(call RESOLVE_PATHS,$(3)); \ + export HLS_IP_INCLUDES=$(call RESOLVE_PATHS,$(6)); \ echo "BUILDER: Staging HLS IP in build directory..."; \ $(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \ cp -rf $(4)/$(1)/* $(5)/$(1); \ cd $(5); \ echo "BUILDER: Building HLS IP..."; \ export VIV_ERR=0; \ - vivado_hls -f $(TOOLS_DIR)/scripts/viv_generate_hls_ip.tcl -l $(1).log || export VIV_ERR=$$?; \ + vivado_hls -f $(call RESOLVE_PATH,$(TOOLS_DIR)/scripts/viv_generate_hls_ip.tcl) -l $(1).log || export VIV_ERR=$$?; \ $(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) release; \ exit $$(($$VIV_ERR)) diff --git a/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl b/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl index f32bfa876..7f4e76b4a 100644 --- a/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl +++ b/fpga/usrp3/tools/scripts/viv_generate_hls_ip.tcl @@ -8,7 +8,12 @@ set part_name $::env(PART_NAME) ;# Full Xilinx part name set hls_ip_name $::env(HLS_IP_NAME) ;# High level synthesis IP name set hls_ip_srcs $::env(HLS_IP_SRCS) ;# High level synthesis IP source files -set hls_ip_inc $::env(HLS_IP_INCLUDES) ;# High level synthesis IP include directories + +if {[info exists env(HLS_IP_INCLUDES)]} { + set hls_ip_inc $::env(HLS_IP_INCLUDES); # High level synthesis IP include directories +} else { + set hls_ip_inc {} +} # --------------------------------------- # Vivado Commands |