| Commit message (Expand) | Author | Age | Files | Lines |
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| * | fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock (... | Matt Ettus | 2010-05-21 | 1 | -1/+8 |
| * | fix double declaration | Matt Ettus | 2010-05-21 | 1 | -1/+0 |
| * | send bigger packets to reduce cpu load | Matt Ettus | 2010-05-20 | 2 | -3/+3 |
| * | put over/underrun on debug bus, remove high order address bits | Matt Ettus | 2010-05-20 | 1 | -1/+2 |
| * | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e | Matt Ettus | 2010-05-20 | 1 | -4/+2 |
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| | * | better debug pins | Matt Ettus | 2010-05-17 | 1 | -6/+4 |
| * | | combined timed and crc cases. fifo pacer produces/consumes at a fixed rate | Matt Ettus | 2010-05-20 | 3 | -34/+48 |
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| * | moved fifos into gpmc_async, reorganized top level a bit, added in crc packet... | Matt Ettus | 2010-05-12 | 6 | -66/+144 |
| * | add missing signal from sensitivity list | Matt Ettus | 2010-05-12 | 1 | -1/+1 |
| * | Merge branch 'master' into u1e | Matt Ettus | 2010-05-12 | 17 | -46/+587 |
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| | * | remove port which is no longer there | Matt Ettus | 2010-05-11 | 1 | -1/+1 |
| | * | cleaned up the logic, this is copied over from quad radio | Matt Ettus | 2010-05-11 | 1 | -13/+5 |
| | * | allow settings bus to cross to a new clock domain, should help timing, but no... | Matt Ettus | 2010-05-11 | 9 | -0/+534 |
| | * | Update config to all eight clock buffers to be used. | Johnathan Corgan | 2010-03-29 | 1 | -1/+1 |
| | * | Added timing constraint for Wishbone clock/dsp_clock skew | Johnathan Corgan | 2010-03-29 | 1 | -0/+2 |
| | * | Merge commit 'upstream/master' | Johnathan Corgan | 2010-03-09 | 1 | -1/+1 |
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| | * | | Cut debug bus connection to etherenet MAC to make closing timing easier | Ian Buckley | 2010-02-24 | 1 | -2/+7 |
| | * | | Remove some warnings in dsp_core_rx | Johnathan Corgan | 2010-02-23 | 1 | -3/+7 |
| | * | | Fix missing item on sensitivity list | Johnathan Corgan | 2010-02-23 | 1 | -1/+1 |
| | * | | Change bit width of CORDIC constants to remove meaningless warning | Johnathan Corgan | 2010-02-23 | 1 | -24/+24 |
| | * | | Manually assign clk_fpga to BUFG to improve timing | Johnathan Corgan | 2010-02-23 | 1 | -1/+5 |
| * | | | packet generator and verifier, to test gpmc and other data transfer stuff | Matt Ettus | 2010-05-12 | 4 | -0/+153 |
| * | | | switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_... | Matt Ettus | 2010-05-10 | 8 | -561/+9 |
| * | | | proper signal level for 24 bit data | Matt Ettus | 2010-05-10 | 1 | -2/+7 |
| * | | | SPI passthru for programming clock gen chip on brand new boards | Matt Ettus | 2010-05-07 | 3 | -0/+391 |
| * | | | added DAC output pins, and a sine wave generator to test them | Matt Ettus | 2010-05-04 | 3 | -18/+63 |
| * | | | Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1e | Matt Ettus | 2010-05-04 | 2 | -0/+14 |
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| | * | | | add timing constraints. Just have main clock signal at 64 MHz for now. | Matt Ettus | 2010-05-04 | 2 | -0/+14 |
| * | | | | changed comment | Matt Ettus | 2010-05-04 | 1 | -1/+1 |
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| * | | | have_space and have_packet now stay high even while busy, | Matt Ettus | 2010-05-03 | 3 | -4/+6 |
| * | | | separate timed tx and rx instead of loopback | Matt Ettus | 2010-04-28 | 1 | -3/+51 |
| * | | | send bus error to debug pins | Matt Ettus | 2010-04-26 | 1 | -2/+4 |
| * | | | Pass previously unused GPIOs to debug pins to help debug interrupts | Matt Ettus | 2010-04-24 | 3 | -16/+21 |
| * | | | Only allow new packets if we can fit the largest possible packet (2KB) | Matt Ettus | 2010-04-23 | 1 | -1/+1 |
| * | | | Register outputs to omap to prevent runt pulses from falsely triggering inter... | Matt Ettus | 2010-04-23 | 3 | -7/+20 |
| * | | | find time_64bit | Matt Ettus | 2010-04-20 | 1 | -0/+1 |
| * | | | added pps and time capability | Matt Ettus | 2010-04-15 | 3 | -5/+21 |
| * | | | access frame length regs from wishbone | Matt Ettus | 2010-04-15 | 2 | -10/+18 |
| * | | | async seems to work with packet lengths now. Still need to do wishbone regs ... | Matt Ettus | 2010-04-15 | 5 | -37/+72 |
| * | | | async gpmc progress | Matt Ettus | 2010-04-15 | 4 | -18/+173 |
| * | | | change time parameters because Xilinx IP has a 1ps timescale | Matt Ettus | 2010-04-15 | 1 | -14/+27 |
| * | | | add bus error reporting | Matt Ettus | 2010-04-15 | 1 | -3/+9 |
| * | | | correct name of module | Matt Ettus | 2010-04-15 | 1 | -2/+2 |
| * | | | progress on synchronous gpmc, but it may not be possible due to the limited n... | Matt Ettus | 2010-04-15 | 3 | -43/+45 |
| * | | | synchronous and asynchronous gpmc models | Matt Ettus | 2010-04-15 | 3 | -3/+100 |
| * | | | handle all tri-state in the top level of gpmc | Matt Ettus | 2010-04-15 | 3 | -6/+8 |
| * | | | more sync progress. This is just a skeleton for now, with junk content | Matt Ettus | 2010-04-14 | 1 | -0/+56 |
| * | | | more progress on synchronous interface | Matt Ettus | 2010-04-14 | 4 | -26/+95 |
| * | | | renamed to async. Will be building a sync version for GPMC_CLK | Matt Ettus | 2010-04-14 | 2 | -3/+3 |
| * | | | make timing diagrams for bus transactions. Still need to do reads | Matt Ettus | 2010-04-14 | 5 | -0/+46 |
