Register outputs to omap to prevent runt pulses from falsely triggering interrupts

3 files changed, 20 insertions, 7 deletions

diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v
index da2051b04..7a3f00483 100644
--- a/usrp2/gpmc/fifo_watcher.v
+++ b/usrp2/gpmc/fifo_watcher.v
@@ -4,7 +4,7 @@ module fifo_watcher
   (input clk, input reset, input clear,
    input src_rdy1, input dst_rdy1, input sof1, input eof1,
    input src_rdy2, input dst_rdy2, input sof2, input eof2,
-   output have_packet, output [15:0] length, output reg bus_error);
+   output reg have_packet, output [15:0] length, output reg bus_error);
 
    wire   write = src_rdy1 & dst_rdy1 & eof1;
    wire   read = src_rdy2 & dst_rdy2 & eof2;
@@ -34,7 +34,11 @@ module fifo_watcher
        bus_error <= 1;
 
    reg 	      in_packet;
-   assign have_packet = have_packet_int & ~in_packet;
+   always @(posedge clk)
+     if(reset | clear)
+       have_packet <= 0;
+     else 
+       have_packet <= have_packet_int & ~in_packet;
    
    always @(posedge clk)
      if(reset | clear)
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index b1a545907..02a00ce57 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -7,7 +7,7 @@ module gpmc_async
    input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
    
    // GPIOs for FIFO signalling
-   output rx_have_data, output tx_have_space, output bus_error, input bus_reset,
+   output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset,
    
    // Wishbone signals
    input wb_clk, input wb_rst,
@@ -31,7 +31,12 @@ module gpmc_async
    assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
 
    wire 	bus_error_tx, bus_error_rx;
-   assign bus_error = bus_error_tx | bus_error_rx;
+
+   always @(posedge fifo_clk)
+     if(fifo_rst)
+       bus_error <= 0;
+     else
+       bus_error <= bus_error_tx | bus_error_rx;
    
    // CS4 is RAM_2PORT for DATA PATH (high-speed data)
    //    Writes go into one RAM, reads come from the other
diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v
index 1df93f910..38f1165fc 100644
--- a/usrp2/gpmc/gpmc_to_fifo_async.v
+++ b/usrp2/gpmc/gpmc_to_fifo_async.v
@@ -5,10 +5,10 @@ module gpmc_to_fifo_async
    input fifo_clk, input fifo_rst,
    output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i,
 
-   input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready,
+   input [15:0] frame_len, input [15:0] fifo_space, output reg fifo_ready,
    output reg bus_error );
 
-   reg [10:0] counter;
+   reg [15:0] counter;
    // Synchronize the async control signals
    reg [1:0] 	cs_del, we_del;
    always @(posedge fifo_clk)
@@ -53,7 +53,11 @@ module gpmc_to_fifo_async
        else
 	 counter <= counter + 1;
 
-   assign fifo_ready = first_write & (fifo_space > frame_len);
+   always @(posedge fifo_clk)
+     if(fifo_rst)
+       fifo_ready <= 0;
+     else
+       fifo_ready <= first_write & (fifo_space > frame_len);
 
    always @(posedge fifo_clk)
      if(fifo_rst)