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| author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-23 10:09:54 -0800 | 
|---|---|---|
| committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2010-02-23 10:09:54 -0800 | 
| commit | 4f66d0fbff3da2105018492d21ca64b96115aba3 (patch) | |
| tree | d958c28c83bc30d797e4f02c6e6d218cc7e2956b /usrp2 | |
| parent | 9519efb38f006e7c934a62f69d7366fe7cdd4410 (diff) | |
| download | uhd-4f66d0fbff3da2105018492d21ca64b96115aba3.tar.gz uhd-4f66d0fbff3da2105018492d21ca64b96115aba3.tar.bz2 uhd-4f66d0fbff3da2105018492d21ca64b96115aba3.zip | |
Remove some warnings in dsp_core_rx
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/sdr_lib/dsp_core_rx.v | 10 | 
1 files changed, 7 insertions, 3 deletions
| diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index af4f0b9fb..aba18fccb 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -32,6 +32,10 @@ module dsp_core_rx     wire        strobe_cic, strobe_hb1, strobe_hb2;     wire        enable_hb1, enable_hb2;     wire [7:0]  cic_decim_rate; + +   wire [31:10] UNUSED_1; +   wire [31:4] 	UNUSED_2; +   wire [31:2] 	UNUSED_3;     setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0       (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), @@ -43,7 +47,7 @@ module dsp_core_rx     setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2       (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), -      .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed()); +      .in(set_data),.out({UNUSED_1, enable_hb1, enable_hb2, cic_decim_rate}),.changed());     rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a       (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -56,12 +60,12 @@ module dsp_core_rx     wire [3:0]  muxctrl;     setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8       (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), -      .in(set_data),.out(muxctrl),.changed()); +      .in(set_data),.out({UNUSED_2,muxctrl}),.changed());     wire [1:0] gpio_ena;     setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9       (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), -      .in(set_data),.out(gpio_ena),.changed()); +      .in(set_data),.out({UNUSED_3,gpio_ena}),.changed());     // The TVRX connects to what is called adc_b, thus A and B are     // swapped throughout the design. | 
