aboutsummaryrefslogtreecommitdiffstats
path: root/usrp2/top/u1e
Commit message (Expand)AuthorAgeFilesLines
* separate clear for tx and rx, and add a global reset from the hostMatt Ettus2011-02-021-10/+19
* usrp-e100: added missing newfifo files to list, added missing signals for timedJosh Blum2011-01-261-1/+2
* usrp-e100: added 32bit test read/write register, fixes to get buildingJosh Blum2011-01-251-7/+17
* reorganized u1e register space to make room for 64 settingregsMatt Ettus2011-01-251-12/+15
* usrp-e100: added readback mux 32 as slave 7 for time readbackJosh Blum2011-01-141-4/+16
* invert led signals because they are active lowMatt Ettus2010-11-091-1/+1
* duhMatt Ettus2010-11-041-1/+1
* watch the ethernet chip select on our debug busMatt Ettus2010-09-233-6/+8
* fix timing issue on DAC outputs with rev 2. This puts the whole system on a ...Matt Ettus2010-09-212-50/+25
* updated pins to match rev2, removed dip switch, etc. seems to compile ok.Matt Ettus2010-09-093-137/+130
* add register to tell host about compatibility level and which image we are usingMatt Ettus2010-08-301-5/+14
* move declaration to make loopback compileMatt Ettus2010-08-271-1/+2
* no need for protocol headers since we're not doing ethernetMatt Ettus2010-08-241-1/+1
* match the signal names in this designMatt Ettus2010-08-231-3/+3
* debug pins cleanupMatt Ettus2010-08-231-3/+3
* properly integrate the new tx chainMatt Ettus2010-08-191-31/+27
* attach run_tx and run_rx to ledsMatt Ettus2010-08-171-1/+1
* connect atrMatt Ettus2010-08-171-1/+1
* delay the q channel to make the channels line up on the AD9862Matt Ettus2010-08-171-1/+6
* this is necessary for some reasonMatt Ettus2010-08-131-1/+2
* connect the setting reg to the real clock and resetMatt Ettus2010-08-111-1/+1
* enlarge loopback fifoMatt Ettus2010-08-101-4/+1
* make loopback compileMatt Ettus2010-07-141-0/+3
* added ability to clear out fifos of tx and rx.Matt Ettus2010-06-171-12/+21
* Merge branch 'master' into u1e_newbuildMatt Ettus2010-06-141-206/+39
* debug pinsMatt Ettus2010-06-101-3/+6
* much bigger fifosMatt Ettus2010-06-101-2/+2
* proper overrun, underrun connections, debug pins.Matt Ettus2010-06-101-4/+8
* debug pinsMatt Ettus2010-06-081-1/+2
* remove double declarationMatt Ettus2010-06-061-1/+1
* use fifo19 not fifo18 in makefileMatt Ettus2010-06-061-1/+1
* use same version as usrp2-udp, so regs are same place in memory mapMatt Ettus2010-06-012-2/+2
* connect the rx run lines so it doesn't get optimized outMatt Ettus2010-06-011-1/+4
* use DDR regs instead of a 2nd clockMatt Ettus2010-06-011-8/+46
* assign addresses for the settings regsMatt Ettus2010-06-011-5/+6
* vita49 tx and rx added in, all sample rates now at main system clock rate.Matt Ettus2010-06-014-107/+220
* send bigger packets to reduce cpu loadMatt Ettus2010-05-201-2/+2
* put over/underrun on debug bus, remove high order address bitsMatt Ettus2010-05-201-1/+2
* Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-201-4/+2
|\
| * better debug pinsMatt Ettus2010-05-171-6/+4
* | combined timed and crc cases. fifo pacer produces/consumes at a fixed rateMatt Ettus2010-05-202-34/+24
|/
* moved fifos into gpmc_async, reorganized top level a bit, added in crc packet...Matt Ettus2010-05-122-22/+43
* switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_...Matt Ettus2010-05-101-1/+1
* proper signal level for 24 bit dataMatt Ettus2010-05-101-2/+7
* added DAC output pins, and a sine wave generator to test themMatt Ettus2010-05-043-18/+63
* Merge branch 'u1e' of ettus.sourcerepo.com:ettus/fpgapriv into u1eMatt Ettus2010-05-042-0/+14
|\
| * add timing constraints. Just have main clock signal at 64 MHz for now.Matt Ettus2010-05-042-0/+14
* | changed commentMatt Ettus2010-05-041-1/+1
|/
* separate timed tx and rx instead of loopbackMatt Ettus2010-04-281-3/+51
* send bus error to debug pinsMatt Ettus2010-04-261-2/+4
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 22:47:15 +0000