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| author | Matt Ettus <matt@ettus.com> | 2010-08-10 09:59:33 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-08-10 09:59:33 -0700 |
| commit | 19974fa00b04280e52d3d644e8e12953c570c06d (patch) | |
| tree | ee56e89e3e6839bf53b68723e23a3fefa6265d85 /usrp2/top/u1e | |
| parent | ea087cc9fbd19ff05893178ea4395cf0f47af61b (diff) | |
| download | uhd-19974fa00b04280e52d3d644e8e12953c570c06d.tar.gz uhd-19974fa00b04280e52d3d644e8e12953c570c06d.tar.bz2 uhd-19974fa00b04280e52d3d644e8e12953c570c06d.zip | |
enlarge loopback fifo
Diffstat (limited to 'usrp2/top/u1e')
| -rw-r--r-- | usrp2/top/u1e/u1e_core.v | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 5b60578ce..516a5cf96 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -101,7 +101,7 @@ module u1e_core wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; `ifdef LOOPBACK - fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo + fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); @@ -437,9 +437,6 @@ module u1e_core { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, { EM_D } }; - //assign debug = { phase[23:8], txsync, txblank, tx }; - - assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, {tx1_src_rdy, tx1_dst_rdy, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; |