Merge branch 'master' into u1e_newbuild

Made so Makefile changes as well to get it to build
* master:
  new make works on ise12
  produces good bin files
  first attempt at cleaning up the build system
  get rid of debug stuff to help timing
  move u2_core into u2_rev3 directory to simplify directory structure and save headaches

Conflicts:
	usrp2/fifo/fifo36_to_fifo18.v
	usrp2/top/u2_rev3/Makefile
	usrp2/top/u2_rev3/Makefile.udp
	usrp2/top/u2_rev3/u2_core_udp.v

1 files changed, 39 insertions, 206 deletions

diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
index cfef1378f..f4a643176 100644
--- a/usrp2/top/u1e/Makefile
+++ b/usrp2/top/u1e/Makefile
@@ -1,37 +1,30 @@
 #
 # Copyright 2008 Ettus Research LLC
-# 
-# This file is part of GNU Radio
-# 
-# GNU Radio is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-# 
-# GNU Radio is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with GNU Radio; see the file COPYING.  If not, write to
-# the Free Software Foundation, Inc., 51 Franklin Street,
-# Boston, MA 02110-1301, USA.
-# 
+#
 
 ##################################################
-# xtclsh Shell and tcl Script Path
+# Project Setup
 ##################################################
-#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
-XTCLSH := xtclsh
-ISE_HELPER := ../tcl/ise_helper.tcl
+TOP_MODULE = u1e
+BUILD_DIR = $(abspath build$(ISE))
 
 ##################################################
-# Project Setup
+# Include other makefiles
 ##################################################
-BUILD_DIR := build/
-export TOP_MODULE := u1e
-export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
+include ../../gpmc/Makefile.srcs
 
 ##################################################
 # Project Properties
@@ -51,159 +44,23 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 ##################################################
 # Sources
 ##################################################
-export SOURCE_ROOT := ../../../
-export SOURCES := \
-control_lib/CRC16_D16.v \
-control_lib/atr_controller16.v \
-control_lib/bin2gray.v \
-control_lib/dcache.v \
-control_lib/decoder_3_8.v \
-control_lib/dpram32.v \
-control_lib/gray2bin.v \
-control_lib/gray_send.v \
-control_lib/icache.v \
-control_lib/mux4.v \
-control_lib/mux8.v \
-control_lib/nsgpio16LE.v \
-control_lib/ram_2port.v \
-control_lib/ram_2port_mixed_width.v \
-control_lib/ram_harv_cache.v \
-control_lib/ram_loader.v \
-control_lib/setting_reg.v \
-control_lib/settings_bus_16LE.v \
-control_lib/srl.v \
-control_lib/system_control.v \
-control_lib/wb_1master.v \
-control_lib/wb_readback_mux.v \
-control_lib/simple_uart.v \
-control_lib/simple_uart_tx.v \
-control_lib/simple_uart_rx.v \
-control_lib/oneshot_2clk.v \
-control_lib/sd_spi.v \
-control_lib/sd_spi_wb.v \
-control_lib/wb_bridge_16_32.v \
-control_lib/reset_sync.v \
-simple_gemac/simple_gemac_wrapper.v \
-simple_gemac/simple_gemac.v \
-simple_gemac/simple_gemac_wb.v \
-simple_gemac/simple_gemac_tx.v \
-simple_gemac/simple_gemac_rx.v \
-simple_gemac/crc.v \
-simple_gemac/delay_line.v \
-simple_gemac/flow_ctrl_tx.v \
-simple_gemac/flow_ctrl_rx.v \
-simple_gemac/address_filter.v \
-simple_gemac/ll8_to_txmac.v \
-simple_gemac/rxmac_to_ll8.v \
-simple_gemac/miim/eth_miim.v \
-simple_gemac/miim/eth_clockgen.v \
-simple_gemac/miim/eth_outputcontrol.v \
-simple_gemac/miim/eth_shiftreg.v \
-control_lib/newfifo/buffer_int.v \
-control_lib/newfifo/buffer_pool.v \
-control_lib/newfifo/fifo_2clock.v \
-control_lib/newfifo/fifo_2clock_cascade.v \
-control_lib/newfifo/ll8_shortfifo.v \
-control_lib/newfifo/ll8_to_fifo36.v \
-control_lib/newfifo/fifo_short.v \
-control_lib/newfifo/fifo_long.v \
-control_lib/newfifo/fifo_cascade.v \
-control_lib/newfifo/fifo36_to_ll8.v \
-control_lib/newfifo/fifo36_to_fifo19.v \
-control_lib/newfifo/fifo19_to_fifo36.v \
-control_lib/newfifo/packet_generator.v \
-control_lib/newfifo/packet_verifier.v \
-control_lib/newfifo/packet_generator32.v \
-control_lib/newfifo/packet_verifier32.v \
-control_lib/newfifo/fifo_pacer.v \
-control_lib/longfifo.v \
-control_lib/shortfifo.v \
-control_lib/medfifo.v \
-coregen/fifo_xlnx_2Kx36_2clk.v \
-coregen/fifo_xlnx_2Kx36_2clk.xco \
-coregen/fifo_xlnx_512x36_2clk.v \
-coregen/fifo_xlnx_512x36_2clk.xco \
-coregen/fifo_xlnx_64x36_2clk.v \
-coregen/fifo_xlnx_64x36_2clk.xco \
-extram/wb_zbt16_b.v \
-opencores/8b10b/decode_8b10b.v \
-opencores/8b10b/encode_8b10b.v \
-opencores/aemb/rtl/verilog/aeMB_bpcu.v \
-opencores/aemb/rtl/verilog/aeMB_core_BE.v \
-opencores/aemb/rtl/verilog/aeMB_ctrl.v \
-opencores/aemb/rtl/verilog/aeMB_edk32.v \
-opencores/aemb/rtl/verilog/aeMB_ibuf.v \
-opencores/aemb/rtl/verilog/aeMB_regf.v \
-opencores/aemb/rtl/verilog/aeMB_xecu.v \
-opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_defines.v \
-opencores/i2c/rtl/verilog/i2c_master_top.v \
-opencores/i2c/rtl/verilog/timescale.v \
-opencores/simple_pic/rtl/simple_pic.v \
-opencores/spi/rtl/verilog/spi_clgen.v \
-opencores/spi/rtl/verilog/spi_defines.v \
-opencores/spi/rtl/verilog/spi_shift.v \
-opencores/spi/rtl/verilog/spi_top16.v \
-sdr_lib/acc.v \
-sdr_lib/add2.v \
-sdr_lib/add2_and_round.v \
-sdr_lib/add2_and_round_reg.v \
-sdr_lib/add2_reg.v \
-sdr_lib/cic_dec_shifter.v \
-sdr_lib/cic_decim.v \
-sdr_lib/cic_int_shifter.v \
-sdr_lib/cic_interp.v \
-sdr_lib/cic_strober.v \
-sdr_lib/clip.v \
-sdr_lib/clip_reg.v \
-sdr_lib/cordic.v \
-sdr_lib/cordic_z24.v \
-sdr_lib/cordic_stage.v \
-sdr_lib/dsp_core_rx_udp.v \
-sdr_lib/dsp_core_tx.v \
-sdr_lib/hb_dec.v \
-sdr_lib/hb_interp.v \
-sdr_lib/round.v \
-sdr_lib/round_reg.v \
-sdr_lib/rx_control.v \
-sdr_lib/rx_dcoffset.v \
-sdr_lib/sign_extend.v \
-sdr_lib/small_hb_dec.v \
-sdr_lib/small_hb_int.v \
-sdr_lib/tx_control.v \
-serdes/serdes.v \
-serdes/serdes_fc_rx.v \
-serdes/serdes_fc_tx.v \
-serdes/serdes_rx.v \
-serdes/serdes_tx.v \
-timing/time_receiver.v \
-timing/time_sender.v \
-timing/time_sync.v \
-timing/timer.v \
-timing/time_64bit.v \
-gpmc/gpmc_async.v \
-gpmc/edge_sync.v \
-gpmc/dbsm.v \
-gpmc/gpmc_to_fifo_async.v \
-gpmc/fifo_to_gpmc_async.v \
-gpmc/fifo_watcher.v \
-gpmc/gpmc_wb.v \
-vrt/vita_rx_control.v \
-vrt/vita_rx_framer.v \
-vrt/vita_tx_control.v \
-vrt/vita_tx_deframer.v \
-timing/time_compare.v \
-top/u1e/u1e_core.v \
-top/u1e/u1e.ucf \
-top/u1e/timing.ucf \
-top/u1e/u1e.v 
+TOP_SRCS = \
+u1e_core.v \
+u1e.v \
+u1e.ucf \
+timing.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPMC_SRCS)
 
 ##################################################
 # Process Properties
 ##################################################
-export SYNTHESIZE_PROPERTIES := \
-"Number of Clock Buffers" 6 \
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
 "Pack I/O Registers into IOBs" Yes \
 "Optimization Effort" High \
 "Optimize Instantiated Primitives" TRUE \
@@ -212,10 +69,10 @@ export SYNTHESIZE_PROPERTIES := \
 "Use Synchronous Reset" Auto \
 "Use Synchronous Set" Auto
 
-export TRANSLATE_PROPERTIES := \
+TRANSLATE_PROPERTIES = \
 "Macro Search Path" "$(shell pwd)/../../coregen/"
 
-export MAP_PROPERTIES := \
+MAP_PROPERTIES = \
 "Allow Logic Optimization Across Hierarchy" TRUE \
 "Map to Input Functions" 4 \
 "Optimization Strategy (Cover Mode)" Speed \
@@ -226,42 +83,18 @@ export MAP_PROPERTIES := \
 "Combinatorial Logic Optimization" TRUE \
 "Register Duplication" TRUE
 
-export PLACE_ROUTE_PROPERTIES := \
+PLACE_ROUTE_PROPERTIES = \
 "Place & Route Effort Level (Overall)" High 
 
-export STATIC_TIMING_PROPERTIES := \
+STATIC_TIMING_PROPERTIES = \
 "Number of Paths in Error/Verbose Report" 10 \
 "Report Type" "Error Report"
 
-export GEN_PROG_FILE_PROPERTIES := \
+GEN_PROG_FILE_PROPERTIES = \
 "Configuration Rate" 6 \
 "Create Binary Configuration File" TRUE \
 "Done (Output Events)" 5 \
 "Enable Bitstream Compression" TRUE \
-"Enable Outputs (Output Events)" 6 \
-"Unused IOB Pins" "Pull Up"
-
-export SIM_MODEL_PROPERTIES := ""
-
-##################################################
-# Make Options
-##################################################
-all:
-	@echo make proj, check, synth, bin, or clean
-
-proj:
-	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
-
-check:
-	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
-
-synth:
-	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
-
-bin:
-	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
-
-clean:
-	rm -rf $(BUILD_DIR)
-
+"Enable Outputs (Output Events)" 6 
 
+SIM_MODEL_PROPERTIES = ""