| Commit message (Expand) | Author | Age | Files | Lines |
* | fpga: x400: Refactor CPLDs build process | Humberto Jimenez | 2021-12-01 | 1 | -4/+8 |
* | fpga: tools: Add Quartus build utilities | Humberto Jimenez | 2021-12-01 | 3 | -0/+163 |
* | fpga: Update help message for setupenv.sh | Wade Fife | 2021-09-10 | 1 | -5/+7 |
* | fpga: tools: Add UHD_FPGA_DIR definition to synthesis | Wade Fife | 2021-09-08 | 3 | -6/+11 |
* | fpga: Set default part for sim in setupenv.sh | Wade Fife | 2021-08-30 | 1 | -5/+4 |
* | fpga: Fix Xilinx bitfile parser for Python 3 | Martin Braun | 2021-08-24 | 1 | -31/+54 |
* | fpga: sim: Add PkgComplex, PkgMath, and PkgRandom | Wade Fife | 2021-08-08 | 1 | -0/+2 |
* | fpga: x400: Add makefiles for RF testbenches | Wade Fife | 2021-06-17 | 1 | -3/+3 |
* | fpga: tools: Detect assertions in ModelSim simulation | Wade Fife | 2021-06-17 | 1 | -2/+22 |
* | fpga: tools: Put SIM_SRCS at end of compile order | Wade Fife | 2021-06-17 | 1 | -1/+1 |
* | fpga: tools: Support new FPGA types in viv_simulator.mak | Wade Fife | 2021-06-17 | 1 | -2/+2 |
* | fpga: tools: Fix python2 reference in viv_ip_builder.mak | Wade Fife | 2021-06-17 | 1 | -1/+1 |
* | fpga: tools: Add modelsim.excludes | Wade Fife | 2021-06-17 | 1 | -0/+18 |
* | fpga: tools: Add modelsim.ini to ModelSim calls | Wade Fife | 2021-06-17 | 4 | -7/+38 |
* | fpga: tools: Add features to run_testbenches.py | Wade Fife | 2021-06-17 | 1 | -6/+19 |
* | fpga: tools: Add ip target to simulation makefiles | Wade Fife | 2021-06-17 | 1 | -2/+5 |
* | fpga: tools: Add X410 support for image packaging | Humberto Jimenez | 2021-06-10 | 1 | -0/+24 |
* | fpga: x400: Add support for X410 motherboard FPGA | Wade Fife | 2021-06-10 | 1 | -0/+2 |
* | fpga: tools: Fix part selection in setupenv | Sam O'Brien | 2021-06-10 | 1 | -4/+12 |
* | fpga: tools: Add ability to run commands before route | Wade Fife | 2021-06-03 | 1 | -5/+11 |
* | fpga: tools: Add ability to patch IP during generation | Wade Fife | 2021-06-03 | 2 | -0/+87 |
* | fpga: tools: Add support for RFSoC | Humberto Jimenez | 2021-06-03 | 2 | -9/+9 |
* | fpga: Remove Python2 support from build system | Martin Braun | 2021-01-04 | 17 | -119/+121 |
* | fpga: Added AA image mappings to N320 | Aaron Rossetto | 2020-09-03 | 1 | -1/+6 |
* | fpga: rfnoc: Remove deprecated files | Wade Fife | 2020-08-23 | 1 | -5/+0 |
* | fpga: tools: RESOLVE_PATH checks for an empty path | Andrew Moch | 2020-07-30 | 1 | -4/+4 |
* | fpga: lib: Add width agnostic version of Ethernet Interface | Andrew Moch | 2020-06-30 | 1 | -0/+1 |
* | fpga: tools: Highlight suppressible errors from vlint | Wade Fife | 2020-06-29 | 1 | -1/+1 |
* | fpga: lib: Add synthesizable AXI4-Stream SV components | Andrew Moch | 2020-06-25 | 1 | -0/+4 |
* | fpga: tools: Fix ModelSim return status | Wade Fife | 2020-06-18 | 2 | -5/+12 |
* | fpga: tools: remove temporary Xilinx directories for BD recreation | Max Köhler | 2020-06-15 | 1 | -10/+13 |
* | fpga: tools: Allow multiple top modules with ModelSim | Wade Fife | 2020-06-11 | 1 | -1/+1 |
* | fpga: tools: Improve detection of setupenv sourcing | Wade Fife | 2020-05-28 | 1 | -29/+31 |
* | fpga: tools: Improve native ModelSim support | Wade Fife | 2020-05-26 | 3 | -72/+255 |
* | fpga: tools: Add contents of directories for HDL source | Wade Fife | 2020-05-26 | 3 | -5/+26 |
* | fpga: tools: Remove uhd_image_builder | Martin Braun | 2020-05-18 | 4 | -1244/+0 |
* | fpga: tools: Fix HLS IP build with Cygwin | Humberto Jimenez | 2020-05-12 | 2 | -4/+10 |
* | fpga: tools: Add -voptargs=+acc to ModelSim GUI | Wade Fife | 2020-04-14 | 1 | -1/+1 |
* | fpga: tools: Option to check for full Vivado version | Humberto Jimenez | 2020-04-14 | 1 | -0/+24 |
* | fpga: tools: Add support for .sdc in Vivado | Paul Butler | 2020-04-02 | 1 | -0/+3 |
* | fpga: tools: Add default Vivado install location | Wade Fife | 2020-04-01 | 1 | -1/+5 |
* | fpga: tools: Add ModelSim to run_testbenches.py | Wade Fife | 2020-03-23 | 1 | -11/+11 |
* | fixup! fpga: tools: Add modelsim to make sim targets | Wade Fife | 2020-03-23 | 1 | -27/+25 |
* | fpga: tools: Add modelsim to make sim targets | Andrew Moch | 2020-03-20 | 3 | -33/+124 |
* | fpga: tools: Ignore BD layout info for TCL-based BD | Humberto Jimenez | 2020-03-12 | 1 | -1/+1 |
* | Merge FPGA repository back into UHD repository | Martin Braun | 2020-01-28 | 43 | -0/+7382 |