| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | fpga: tools: Add Quartus build utilities | Humberto Jimenez | 2021-12-01 | 3 | -0/+163 |
| * | fpga: tools: Add UHD_FPGA_DIR definition to synthesis | Wade Fife | 2021-09-08 | 2 | -4/+5 |
| * | fpga: Set default part for sim in setupenv.sh | Wade Fife | 2021-08-30 | 1 | -5/+4 |
| * | fpga: sim: Add PkgComplex, PkgMath, and PkgRandom | Wade Fife | 2021-08-08 | 1 | -0/+2 |
| * | fpga: tools: Support new FPGA types in viv_simulator.mak | Wade Fife | 2021-06-17 | 1 | -2/+2 |
| * | fpga: tools: Fix python2 reference in viv_ip_builder.mak | Wade Fife | 2021-06-17 | 1 | -1/+1 |
| * | fpga: tools: Add modelsim.ini to ModelSim calls | Wade Fife | 2021-06-17 | 1 | -0/+2 |
| * | fpga: tools: Add ip target to simulation makefiles | Wade Fife | 2021-06-17 | 1 | -2/+5 |
| * | fpga: tools: Add ability to patch IP during generation | Wade Fife | 2021-06-03 | 1 | -0/+33 |
| * | fpga: Remove Python2 support from build system | Martin Braun | 2021-01-04 | 3 | -7/+7 |
| * | fpga: tools: RESOLVE_PATH checks for an empty path | Andrew Moch | 2020-07-30 | 1 | -4/+4 |
| * | fpga: tools: remove temporary Xilinx directories for BD recreation | Max Köhler | 2020-06-15 | 1 | -10/+13 |
| * | fpga: tools: Allow multiple top modules with ModelSim | Wade Fife | 2020-06-11 | 1 | -1/+1 |
| * | fpga: tools: Improve native ModelSim support | Wade Fife | 2020-05-26 | 1 | -72/+38 |
| * | fpga: tools: Add contents of directories for HDL source | Wade Fife | 2020-05-26 | 1 | -1/+1 |
| * | fpga: tools: Fix HLS IP build with Cygwin | Humberto Jimenez | 2020-05-12 | 1 | -3/+4 |
| * | fpga: tools: Add -voptargs=+acc to ModelSim GUI | Wade Fife | 2020-04-14 | 1 | -1/+1 |
| * | fixup! fpga: tools: Add modelsim to make sim targets | Wade Fife | 2020-03-23 | 1 | -27/+25 |
| * | fpga: tools: Add modelsim to make sim targets | Andrew Moch | 2020-03-20 | 2 | -19/+106 |
| * | Merge FPGA repository back into UHD repository | Martin Braun | 2020-01-28 | 6 | -0/+418 |
