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| author | Martin Braun <martin.braun@ettus.com> | 2020-12-01 18:50:12 +0100 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-01-04 13:28:36 -0600 |
| commit | ca68195b5d12c5410cfac8d459a0b0902c4c72c7 (patch) | |
| tree | d50d2bd7541000fa0a0470c4f1f4610c93d3b410 /fpga/usrp3/tools/make | |
| parent | 3b9ced8f07c068faf1f494ce170cb44edaa47075 (diff) | |
| download | uhd-ca68195b5d12c5410cfac8d459a0b0902c4c72c7.tar.gz uhd-ca68195b5d12c5410cfac8d459a0b0902c4c72c7.tar.bz2 uhd-ca68195b5d12c5410cfac8d459a0b0902c4c72c7.zip | |
fpga: Remove Python2 support from build system
- 2to3 was used to convert the Python scripts, except where the tool
choked and manual intervention was required
- All references to "python" where replaced with "python3"
- buffer() was replaced by memoryview()
Diffstat (limited to 'fpga/usrp3/tools/make')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_design_builder.mak | 4 | ||||
| -rw-r--r-- | fpga/usrp3/tools/make/viv_ip_builder.mak | 8 | ||||
| -rw-r--r-- | fpga/usrp3/tools/make/viv_preamble.mak | 2 |
3 files changed, 7 insertions, 7 deletions
diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak index 5a54da012..74f1ef034 100644 --- a/fpga/usrp3/tools/make/viv_design_builder.mak +++ b/fpga/usrp3/tools/make/viv_design_builder.mak @@ -22,7 +22,7 @@ BUILD_VIVADO_DESIGN = \ export VIV_TOOLS_DIR=$(call RESOLVE_PATH,$(TOOLS_DIR)); \ export VIV_OUTPUT_DIR=$(call RESOLVE_PATH,$(BUILD_DIR)); \ export VIV_TOP_MODULE=$(2); \ - export VIV_PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ + export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \ @@ -47,7 +47,7 @@ CHECK_VIVADO_DESIGN = \ export VIV_TOOLS_DIR=$(call RESOLVE_PATH,$(TOOLS_DIR)); \ export VIV_OUTPUT_DIR=$(call RESOLVE_PATH,$(BUILD_DIR)); \ export VIV_TOP_MODULE=$(2); \ - export VIV_PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ + export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \ diff --git a/fpga/usrp3/tools/make/viv_ip_builder.mak b/fpga/usrp3/tools/make/viv_ip_builder.mak index c30484d17..e2ca66cd5 100644 --- a/fpga/usrp3/tools/make/viv_ip_builder.mak +++ b/fpga/usrp3/tools/make/viv_ip_builder.mak @@ -25,7 +25,7 @@ BUILD_VIVADO_IP = \ echo "BUILDER: Building IP $(1)"; \ echo "========================================================"; \ export XCI_FILE=$(call RESOLVE_PATH,$(5)/$(1)/$(1).xci); \ - export PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \ + export PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \ export GEN_EXAMPLE=$(6); \ export SYNTH_IP=$(SYNTH_IP); \ echo "BUILDER: Staging IP in build directory..."; \ @@ -34,7 +34,7 @@ BUILD_VIVADO_IP = \ $(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \ cp -rf $(4)/$(1)/* $(5)/$(1); \ echo "BUILDER: Retargeting IP to part $(2)/$(3)..."; \ - python $(TOOLS_DIR)/scripts/viv_ip_xci_editor.py --output_dir=$(5)/$(1) --target=$(2)/$(3) retarget $(4)/$(1)/$(1).xci; \ + python3 $(TOOLS_DIR)/scripts/viv_ip_xci_editor.py --output_dir=$(5)/$(1) --target=$(2)/$(3) retarget $(4)/$(1)/$(1).xci; \ cd $(5); \ echo "BUILDER: Building IP..."; \ export VIV_ERR=0; \ @@ -58,7 +58,7 @@ BUILD_VIVADO_BD = \ echo "BUILDER: Building BD $(1)"; \ echo "========================================================"; \ export BD_FILE=$(call RESOLVE_PATH,$(5)/$(1)/$(1).bd); \ - export PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \ + export PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \ echo "BUILDER: Staging BD in build directory..."; \ rm -rf $(5)/$(1); \ mkdir -p $(5)/$(1); \ @@ -90,7 +90,7 @@ BUILD_VIVADO_BDTCL = \ echo "BUILDER: Generating BD from Tcl $(1)"; \ echo "========================================================"; \ export BD_FILE=$(call RESOLVE_PATH,$(5)/$(1)/$(1).tcl); \ - export PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \ + export PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \ export BD_IP_REPOS=$(call RESOLVE_PATH,$(6)); \ export BD_HDL_SRCS=$(call RESOLVE_PATHS,$(7)); \ echo "BUILDER: Staging BD Tcl in build directory..."; \ diff --git a/fpga/usrp3/tools/make/viv_preamble.mak b/fpga/usrp3/tools/make/viv_preamble.mak index 87115934b..ab9e01756 100644 --- a/fpga/usrp3/tools/make/viv_preamble.mak +++ b/fpga/usrp3/tools/make/viv_preamble.mak @@ -55,7 +55,7 @@ endif .check_tool: @echo "BUILDER: Checking tools..." @echo -n "* "; bash --version | grep bash || (echo "ERROR: Bash not found in environment. Please install it"; exit 1;) - @echo -n "* "; python --version || (echo "ERROR: Python not found in environment. Please install it"; exit 1;) + @echo -n "* "; python3 --version || (echo "ERROR: Python not found in environment. Please install it"; exit 1;) @echo -n "* "; vivado -version 2>&1 | grep Vivado || (echo "ERROR: Vivado not found in environment. Please run setupenv.sh"; exit 1;) # ------------------------------------------------------------------- |