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| author | Wade Fife <wade.fife@ettus.com> | 2021-09-01 15:27:45 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-09-08 08:36:05 -0500 |
| commit | 66267f515802ff3f965fd44e1f0d3097ada7484f (patch) | |
| tree | 909154ba1870a25d17dbe08323863b41613240bf /fpga/usrp3/tools/make | |
| parent | e3072176b0990aa17a62768d2d1cb62141898308 (diff) | |
| download | uhd-66267f515802ff3f965fd44e1f0d3097ada7484f.tar.gz uhd-66267f515802ff3f965fd44e1f0d3097ada7484f.tar.bz2 uhd-66267f515802ff3f965fd44e1f0d3097ada7484f.zip | |
fpga: tools: Add UHD_FPGA_DIR definition to synthesis
This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to
the location of the UHD "fpga" directory. This allows you to include
files in your out-of-tree modules relative to the FPGA directory. For
example, you could include the library header file rfnoc_chdr_utils.vh
using the following:
`include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
Some simulators may not support `" outside of the context of a `define,
in which case you can do the following:
`define RFNOC_CHDR_UTILS_PATH \
`"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
`include `RFNOC_CHDR_UTILS_PATH
Diffstat (limited to 'fpga/usrp3/tools/make')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_design_builder.mak | 4 | ||||
| -rw-r--r-- | fpga/usrp3/tools/make/viv_simulator.mak | 5 |
2 files changed, 5 insertions, 4 deletions
diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak index 74f1ef034..3ca44b01b 100644 --- a/fpga/usrp3/tools/make/viv_design_builder.mak +++ b/fpga/usrp3/tools/make/viv_design_builder.mak @@ -25,7 +25,7 @@ BUILD_VIVADO_DESIGN = \ export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ - export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \ + export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \ cd $(BUILD_DIR); \ $(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou @@ -50,7 +50,7 @@ CHECK_VIVADO_DESIGN = \ export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ - export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \ + export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)../../"; \ cd $(BUILD_DIR); \ $(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(TOOLS_DIR)/scripts/check_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou diff --git a/fpga/usrp3/tools/make/viv_simulator.mak b/fpga/usrp3/tools/make/viv_simulator.mak index 64af051a1..c49c05cba 100644 --- a/fpga/usrp3/tools/make/viv_simulator.mak +++ b/fpga/usrp3/tools/make/viv_simulator.mak @@ -52,6 +52,7 @@ SETUP_AND_LAUNCH_SIMULATION = \ export VIV_SIM_USER_DO=$(MODELSIM_USER_DO); \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_SIM_64BIT=$(MODELSIM_64BIT); \ + export VIV_VERILOG_DEFS="UHD_FPGA_DIR=$(BASE_DIR)/../.."; \ $(TOOLS_DIR)/scripts/launch_vivado.sh -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(TOOLS_DIR)/scripts/viv_sim_project.tcl) -log xsim.log -nojournal # ------------------------------------------------------------------- @@ -65,8 +66,8 @@ SETUP_AND_LAUNCH_VLINT = \ export VLINT_DESIGN_SRCS=$(EXP_DESIGN_SRCS); \ export VLINT_SIM_SRCS=$(EXP_SIM_SRCS); \ export VLINT_INC_SRCS=$(EXP_INC_SRCS); \ - export VLINT_SVLOG_ARGS="$(SVLOG_ARGS)"; \ - export VLINT_VLOG_ARGS="$(VLOG_ARGS)"; \ + export VLINT_SVLOG_ARGS="$(SVLOG_ARGS) +define+UHD_FPGA_DIR=$(BASE_DIR)/../.."; \ + export VLINT_VLOG_ARGS="$(VLOG_ARGS) +define+UHD_FPGA_DIR=$(BASE_DIR)/../.."; \ export VLINT_VHDL_ARGS="$(VHDL_ARGS)"; \ export VLINT_MODELSIM_INI="$(MODELSIM_INI)"; \ $(TOOLS_DIR)/scripts/launch_vlint.sh |