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| | * allow setting time immediately in cases where there is no external pps inputMatt Ettus2010-01-181-4/+5
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| | * allow processor to read back vrt time over readback muxMatt Ettus2010-01-181-2/+2
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| | * proper time sync to ppsMatt Ettus2010-01-182-5/+30
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| * | just debug pin changesMatt Ettus2010-01-252-1/+12
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| * | typo caused the tx udp chain to be disconnectedMatt Ettus2010-01-231-1/+1
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| * | moved into subdirJosh Blum2010-01-22661-491/+0
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| * | should fix the endless packet bugMatt Ettus2010-01-181-1/+3
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| * | yet another typoMatt Ettus2010-01-151-1/+1
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| * | yet more debug linesMatt Ettus2010-01-152-4/+9
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| * | typoMatt Ettus2010-01-151-1/+1
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| * | add debug pins to find the problem with lost eof in the udp coreMatt Ettus2010-01-151-2/+2
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| * | try a width that works...Matt Ettus2010-01-141-1/+2
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| * | try proper resetMatt Ettus2010-01-141-1/+1
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| * | forgot to declare wireMatt Ettus2010-01-141-1/+3
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| * | debug stateMatt Ettus2010-01-143-5/+12
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| * | empty file, it is actually located in the control directoryMatt Ettus2010-01-141-0/+0
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| * | make it match the 36 bit wide versionMatt Ettus2010-01-142-6/+8
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| * | better debug pinsMatt Ettus2010-01-052-9/+9
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| * | more typo fixes.Matt Ettus2010-01-051-3/+3
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| * | typo fixMatt Ettus2010-01-051-1/+1
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| * | actually connect the ports -- why this isn't flagged as an error I'll never knowMatt Ettus2010-01-051-3/+8
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| * | place udp core in the memory spaceMatt Ettus2010-01-052-9/+12
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| * | Merge branch 'wip/usrp2' of http://gnuradio.org/git/matt into wip/usrp2Josh Blum2010-01-052-5/+30
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| | * | proper time sync to ppsMatt Ettus2009-12-222-5/+30
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| * | Merge branch 'udp' of http://gnuradio.org/git/matt into wip/usrp2Josh Blum2010-01-0513-49/+1073
| |\ \ | | |/ | |/| | | | | | | Conflicts: usrp2/fpga/top/u2_rev3/Makefile
| | * never should have checked in this generated binary fileMatt Ettus2009-12-211-21251/+0
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| | * barebones udp support. Compiles, but untested.Matt Ettus2009-12-219-18/+538
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| | * 19-bit fifo handling for receive side of eth/udp systemMatt Ettus2009-12-212-45/+83
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| | * 19 bit wide interface in prep for connection to UDP/IP state machines.Matt Ettus2009-12-215-0/+21717
| |/ |/| | | | | TX side done, not rx yet. Not tested, but it does compile.
| * cleaned up the main ibs state machineMatt Ettus2009-12-141-9/+22
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| * dsp_core_tx now has setting reg base settable from u2_core. underrun bug in ↵Matt Ettus2009-12-143-10/+9
| | | | | | | | vrt fixed
| * changed debug pins to see incoming dataMatt Ettus2009-12-121-3/+4
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| * reorder the memory mapMatt Ettus2009-12-112-2/+2
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| * put new setting reg into the address space in the right placeMatt Ettus2009-12-111-1/+1
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| * only pull from input fifo when really consuming or pushing into the next fifoMatt Ettus2009-12-111-1/+1
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| * Add ability to clear state out when there is an underrunMatt Ettus2009-12-111-1/+6
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| * fixed typo in u2_core.v resulting in unconnected net. added debug pinsMatt Ettus2009-12-113-14/+35
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| * ignore save filesMatt Ettus2009-12-091-0/+1
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| * First cut at vita tx, whole thing compilesMatt Ettus2009-12-093-27/+37
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| * flag packets which arrive way too early so the device doesn't sit there forever.Matt Ettus2009-12-091-2/+4
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| * very basic packet sending worksMatt Ettus2009-12-092-140/+50
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| * seems to correctly deframe packets. now need to consume them.Matt Ettus2009-12-081-12/+23
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| * progress on vita_tx. it compiles now, need to work on vita_tx_control.Matt Ettus2009-12-083-239/+182
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| * make the testbench work in this environment, without the crossclock settings busMatt Ettus2009-12-083-5/+8
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| * be a little more PC about itMatt Ettus2009-11-181-5/+9
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| * mostly just copied over from the rx side. Still needs a lot of work.Matt Ettus2009-11-183-13/+221
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| * forgot to declare wiresMatt Ettus2009-11-061-0/+4
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| * moved regs around for vita49Matt Ettus2009-11-052-12/+13
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| * vita rx instead of rx_control. Ready for firmware testing. Misses timing ↵Matt Ettus2009-11-054-4/+48
| | | | | | | | by a little bit, will worry later.
| * put 64 bit timer for vita49 on the settings busMatt Ettus2009-11-053-8/+17
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