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| author | Matt Ettus <matt@ettus.com> | 2010-01-18 16:07:48 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-01-18 16:07:48 -0800 |
| commit | 3df028c652bb5e138aeb9cbc3e26bd26ab314120 (patch) | |
| tree | b146b223764a2da51cedd9cb423916719a06db1f | |
| parent | 1dc61299faa55e13e535fe20a035aed664084b16 (diff) | |
| download | uhd-3df028c652bb5e138aeb9cbc3e26bd26ab314120.tar.gz uhd-3df028c652bb5e138aeb9cbc3e26bd26ab314120.tar.bz2 uhd-3df028c652bb5e138aeb9cbc3e26bd26ab314120.zip | |
allow processor to read back vrt time over readback mux
| -rw-r--r-- | top/u2_core/u2_core.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index 2fa490d26..8cd150cb6 100644 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -412,8 +412,8 @@ module u2_core .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), - .word11(32'b0),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), + .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) ); // ///////////////////////////////////////////////////////////////////////// |