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| author | Matt Ettus <matt@ettus.com> | 2009-12-08 22:58:49 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-12-08 22:58:49 -0800 |
| commit | 2de05770dfa11bfbe787a9d9e442d898980fb06a (patch) | |
| tree | d8094d9a4c26d754210e991cf1eb35f7921d9659 | |
| parent | f31b84fb006ca7614a5fe1885b6e5b1cdc25d2a5 (diff) | |
| download | uhd-2de05770dfa11bfbe787a9d9e442d898980fb06a.tar.gz uhd-2de05770dfa11bfbe787a9d9e442d898980fb06a.tar.bz2 uhd-2de05770dfa11bfbe787a9d9e442d898980fb06a.zip | |
make the testbench work in this environment, without the crossclock settings bus
| -rw-r--r-- | vrt/.gitignore | 1 | ||||
| -rwxr-xr-x | vrt/vita_rx.build | 2 | ||||
| -rw-r--r-- | vrt/vita_rx_tb.v | 10 |
3 files changed, 8 insertions, 5 deletions
diff --git a/vrt/.gitignore b/vrt/.gitignore index 14460fbdc..560066de5 100644 --- a/vrt/.gitignore +++ b/vrt/.gitignore @@ -1,2 +1,3 @@ vita_rx_tb +vita_tx_tb *.vcd diff --git a/vrt/vita_rx.build b/vrt/vita_rx.build index e25e1b4e1..f6d2d75a3 100755 --- a/vrt/vita_rx.build +++ b/vrt/vita_rx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v +iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v diff --git a/vrt/vita_rx_tb.v b/vrt/vita_rx_tb.v index bc62c6898..b4fda9622 100644 --- a/vrt/vita_rx_tb.v +++ b/vrt/vita_rx_tb.v @@ -29,24 +29,26 @@ module vita_rx_tb; wire [7:0] set_addr_dsp; wire [31:0] set_data_dsp; + /* settings_bus_crossclock settings_bus_xclk_dsp (.clk_i(clk), .rst_i(reset), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data), .clk_o(clk), .rst_o(reset), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp)); - + */ + wire sample_dst_rdy, sample_src_rdy; //wire [99:0] sample_data_o; wire [64+4+(MAXCHAN*32)-1:0] sample_data_o; vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control (.clk(clk), .reset(reset), .clear(0), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .vita_time(vita_time), .overrun(overrun), .sample_fifo_o(sample_data_o), .sample_fifo_dst_rdy_i(sample_dst_rdy), .sample_fifo_src_rdy_o(sample_src_rdy), .sample(sample), .run(run), .strobe(strobe)); vita_rx_framer #(.BASE(0), .MAXCHAN(MAXCHAN)) vita_rx_framer (.clk(clk), .reset(reset), .clear(0), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .data_o(data_o), .dst_rdy_i(dst_rdy), .src_rdy_o(src_rdy), .sample_fifo_i(sample_data_o), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy), .fifo_occupied(), .fifo_full(), .fifo_empty() ); @@ -61,7 +63,7 @@ module vita_rx_tb; time_64bit #(.TICKS_PER_SEC(120000000), .BASE(0)) time_64bit (.clk(clk), .rst(reset), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .pps(0), .vita_time(vita_time)); always @(posedge clk) |