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* allow processor to read back vrt time over readback muxMatt Ettus2010-01-181-2/+2
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* proper time sync to ppsMatt Ettus2010-01-182-5/+30
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* cleaned up the main ibs state machineMatt Ettus2009-12-141-9/+22
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* dsp_core_tx now has setting reg base settable from u2_core. underrun bug in ↵Matt Ettus2009-12-143-10/+9
| | | | vrt fixed
* changed debug pins to see incoming dataMatt Ettus2009-12-121-3/+4
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* reorder the memory mapMatt Ettus2009-12-112-2/+2
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* put new setting reg into the address space in the right placeMatt Ettus2009-12-111-1/+1
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* only pull from input fifo when really consuming or pushing into the next fifoMatt Ettus2009-12-111-1/+1
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* Add ability to clear state out when there is an underrunMatt Ettus2009-12-111-1/+6
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* fixed typo in u2_core.v resulting in unconnected net. added debug pinsMatt Ettus2009-12-113-14/+35
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* ignore save filesMatt Ettus2009-12-091-0/+1
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* First cut at vita tx, whole thing compilesMatt Ettus2009-12-093-27/+37
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* flag packets which arrive way too early so the device doesn't sit there forever.Matt Ettus2009-12-091-2/+4
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* very basic packet sending worksMatt Ettus2009-12-092-140/+50
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* seems to correctly deframe packets. now need to consume them.Matt Ettus2009-12-081-12/+23
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* progress on vita_tx. it compiles now, need to work on vita_tx_control.Matt Ettus2009-12-083-239/+182
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* make the testbench work in this environment, without the crossclock settings busMatt Ettus2009-12-083-5/+8
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* be a little more PC about itMatt Ettus2009-11-181-5/+9
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* mostly just copied over from the rx side. Still needs a lot of work.Matt Ettus2009-11-183-13/+221
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* forgot to declare wiresMatt Ettus2009-11-061-0/+4
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* moved regs around for vita49Matt Ettus2009-11-052-12/+13
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* vita rx instead of rx_control. Ready for firmware testing. Misses timing ↵Matt Ettus2009-11-054-4/+48
| | | | by a little bit, will worry later.
* put 64 bit timer for vita49 on the settings busMatt Ettus2009-11-053-8/+17
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* VITA49 rx (and tx skeleton) copied over from quad radioMatt Ettus2009-11-057-0/+1026
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* This branch is for porting from the quad radio, and minor text cleanupsMatt Ettus2009-11-044-15/+259
| | | | | | The counter is for performance monitoring in firmware, priority encoder and new interrupt controller are from quad radio and speed up interrupts. This is tested and it works for me.
* earliest beta files renamed to avoid confusionMatt Ettus2009-10-116-0/+0
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* Properly reset the fifos. We didn't connect before.Matt Ettus2009-10-051-5/+5
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* Merge branch 'new_eth' of http://gnuradio.org/git/matt into masterJohnathan Corgan2009-10-01613-90023/+2518
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'new_eth' of http://gnuradio.org/git/matt: (42 commits) Fix warnings, mostly from implicitly defined wires or unspecified widths fullchip sim now compiles again, after moving eth and models over to new simple_gemac remove unused opencores remove debugging code no idea where this came from, it shouldn't be here Copied wb_1master back from quad radio Remove old mac. Good riddance. remove unused port More xilinx fifos, more clean up of our fifos might as well use a cascade fifo to help timing and give a little more capacity fix a typo which caused tx glitches Untested fixes for getting serdes onto the new fifo system. Compiles, at least Implement Eth flow control using pause frames parameterized fifo sizes, some reformatting remove unused old style fifo allow control of whether or not to honor flow control, adds some debug lines debug the rx side no longer used, replaced by newfifo version remove special last_line adjustment from ethernet port Firmware now inserts mac source address value in each frame. ...
| * Fix warnings, mostly from implicitly defined wires or unspecified widthsMatt Ettus2009-10-016-8/+14
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| * fullchip sim now compiles again, after moving eth and models over to new ↵Matt Ettus2009-10-015-17/+159
| | | | | | | | simple_gemac
| * remove unused opencoresMatt Ettus2009-10-01463-71885/+0
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| * Merge branch 'new_wb_intercon' into new_ethMatt Ettus2009-09-302-224/+239
| |\ | | | | | | | | | | | | | | | | | | Functionality should not change at all Conflicts: usrp2/fpga/top/u2_core/u2_core.v
| | * Copied wb_1master back from quad radioMatt Ettus2009-09-302-223/+238
| | | | | | | | | | | | more sane config options, should be exactly the same memory map
| * | no idea where this came from, it shouldn't be hereMatt Ettus2009-09-301-1/+1
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| * | Merge commit 'origin' into new_ethMatt Ettus2009-09-243-11/+24
| |\| | | | | | | | | | | | | Conflicts: .gitignore
| * | Merge branch 'serdes_newfifo' into new_ethMatt Ettus2009-09-203-79/+30
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| | * | Untested fixes for getting serdes onto the new fifo system. Compiles, at leastMatt Ettus2009-09-043-79/+30
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| * | | Remove old mac. Good riddance.Matt Ettus2009-09-1064-15211/+0
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| * | | remove unused portMatt Ettus2009-09-101-1/+1
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| * | | More xilinx fifos, more clean up of our fifosMatt Ettus2009-09-1012-129/+555
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| * | | might as well use a cascade fifo to help timing and give a little more capacityMatt Ettus2009-09-101-1/+1
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| * | | fix a typo which caused tx glitchesMatt Ettus2009-09-051-1/+1
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| * | Implement Eth flow control using pause framesMatt Ettus2009-09-045-73/+66
| | | | | | | | | | | | | | | | | | Not fully tested, but it seems to work without frame errors, sequence number errors or ethernet overruns. Still of course will get tx underruns on a slow machine, and the transmitted signal has some issues though.
| * | parameterized fifo sizes, some reformattingMatt Ettus2009-09-042-54/+57
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| * | remove unused old style fifoMatt Ettus2009-09-041-31/+0
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| * | allow control of whether or not to honor flow control, adds some debug linesMatt Ettus2009-09-041-6/+16
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| * | debug the rx sideMatt Ettus2009-09-041-1/+6
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| * | no longer used, replaced by newfifo versionMatt Ettus2009-09-041-66/+0
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| * | seems to build a decent fpga, but still some issues with a full connection.Matt Ettus2009-09-033-29/+36
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| * | MAC transmit seems to work now. The root cause of the problem was ↵Matt Ettus2009-09-034-67/+70
| | | | | | | | | | | | accidentally using the rx_clk in one stage of the fifos on the tx side.
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