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| author | Matt Ettus <matt@ettus.com> | 2009-09-10 11:40:18 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-09-10 11:40:18 -0700 |
| commit | 38e0c588af094e7f809ad73981a3ba002d2c936d (patch) | |
| tree | e6727f5841cb8dc1d511ef1ce32135af9435c59a | |
| parent | eee63907c03961549eb377ffd933407fb9b9a651 (diff) | |
| download | uhd-38e0c588af094e7f809ad73981a3ba002d2c936d.tar.gz uhd-38e0c588af094e7f809ad73981a3ba002d2c936d.tar.bz2 uhd-38e0c588af094e7f809ad73981a3ba002d2c936d.zip | |
might as well use a cascade fifo to help timing and give a little more capacity
| -rw-r--r-- | simple_gemac/simple_gemac_wrapper.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v index 7511f3fb9..71ad0cf0f 100644 --- a/simple_gemac/simple_gemac_wrapper.v +++ b/simple_gemac/simple_gemac_wrapper.v @@ -110,7 +110,7 @@ module simple_gemac_wrapper wire [35:0] tx_f36_data_int1; wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; - fifo_2clock #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo + fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), .rclk(tx_clk), .dataout(tx_f36_data_int1), |