diff options
Diffstat (limited to 'usrp2/top/u1plus/core_compile')
| -rwxr-xr-x | usrp2/top/u1plus/core_compile | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/usrp2/top/u1plus/core_compile b/usrp2/top/u1plus/core_compile index 0d95f704d..b2ccc8b49 100755 --- a/usrp2/top/u1plus/core_compile +++ b/usrp2/top/u1plus/core_compile @@ -1,2 +1 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ u1plus_core.v 2>&1 - +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |