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| author | Matt Ettus <matt@ettus.com> | 2011-03-17 12:23:20 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:21 -0700 |
| commit | 262c6e9225889a1ff4afd045ad0c6d929d06478c (patch) | |
| tree | 9e5b522c857bb07525a6ff91b47c5e43143ca369 /usrp2/top/u1plus/core_compile | |
| parent | fd2f7f333a643f070a9f9c19228ea83c15c875fb (diff) | |
| download | uhd-262c6e9225889a1ff4afd045ad0c6d929d06478c.tar.gz uhd-262c6e9225889a1ff4afd045ad0c6d929d06478c.tar.bz2 uhd-262c6e9225889a1ff4afd045ad0c6d929d06478c.zip | |
u1p: added loopback and timed capability just like u1e
Diffstat (limited to 'usrp2/top/u1plus/core_compile')
| -rwxr-xr-x | usrp2/top/u1plus/core_compile | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/usrp2/top/u1plus/core_compile b/usrp2/top/u1plus/core_compile index 0d95f704d..b2ccc8b49 100755 --- a/usrp2/top/u1plus/core_compile +++ b/usrp2/top/u1plus/core_compile @@ -1,2 +1 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ u1plus_core.v 2>&1 - +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |