diff options
Diffstat (limited to 'fpga/usrp3/top/x400/regmap')
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/PkgRFDC_REGS_REGMAP.vhd | 663 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/axi_hpm0_regmap_utils.vh | 110 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/core_regs_regmap_utils.vh | 41 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/cpld_interface_regmap_utils.vh | 71 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/dio_regmap_utils.vh | 69 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/global_regs_regmap_utils.vh | 276 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/pl_cpld_regmap_utils.vh | 41 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh | 31 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/rfdc_regs_regmap_utils.vh | 303 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/rfdc_timing_regmap_utils.vh | 45 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh | 153 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/regmap/versioning_utils.vh | 109 |
12 files changed, 1912 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x400/regmap/PkgRFDC_REGS_REGMAP.vhd b/fpga/usrp3/top/x400/regmap/PkgRFDC_REGS_REGMAP.vhd new file mode 100644 index 000000000..c5732d01f --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/PkgRFDC_REGS_REGMAP.vhd @@ -0,0 +1,663 @@ +--------------------------------------------------------------------- +-- +-- Copyright 2021 Ettus Research, A National Instruments Brand +-- SPDX-License-Identifier: LGPL-3.0-or-later +-- +-- Module: PkgRFDC_REGS_REGMAP.vhd +-- +-- Purpose: +-- The constants in this file are autogenerated by XmlParse. +-- +---------------------------------------------------------------------- +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package PkgRFDC_REGS_REGMAP is + +--=============================================================================== +-- A numerically ordered list of registers and their HDL source files +--=============================================================================== + + -- MMCM : 0x0 (common_regs.v) + -- INVERT_IQ_REG : 0x10000 (common_regs.v) + -- MMCM_RESET_REG : 0x11000 (common_regs.v) + -- RF_RESET_CONTROL_REG : 0x12000 (common_regs.v) + -- RF_RESET_STATUS_REG : 0x12008 (common_regs.v) + -- RF_AXI_STATUS_REG : 0x13000 (common_regs.v) + -- FABRIC_DSP_REG : 0x13008 (common_regs.v) + -- CALIBRATION_DATA : 0x14000 (common_regs.v) + -- CALIBRATION_ENABLE : 0x14008 (common_regs.v) + -- THRESHOLD_STATUS : 0x15000 (common_regs.v) + -- RF_PLL_CONTROL_REG : 0x16000 (common_regs.v) + -- RF_PLL_STATUS_REG : 0x16008 (common_regs.v) + +--=============================================================================== +-- RegTypes +--=============================================================================== + +--=============================================================================== +-- Register Group RFDC_REGS +--=============================================================================== + + -- Enumerated type FABRIC_DSP_BW_ENUM + constant kFABRIC_DSP_BW_ENUMSize : integer := 4; + constant kFABRIC_DSP_BW_NONE : integer := 0; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_NONE + constant kFABRIC_DSP_BW_100M : integer := 100; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_100M + constant kFABRIC_DSP_BW_200M : integer := 200; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_200M + constant kFABRIC_DSP_BW_400M : integer := 400; -- FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_400M + + -- MMCM Window (from common_regs.v) + constant kMMCM : integer := 16#0#; -- Window Offset + constant kMMCMSize: integer := 16#10000#; -- size in bytes + --function kMMCMRec return XReg2_t; -- Window Record function commented out due to programmable attributes + + -- INVERT_IQ_REG Register (from common_regs.v) + constant kINVERT_IQ_REG : integer := 16#10000#; -- Register Offset + constant kINVERT_IQ_REGSize: integer := 32; -- register width in bits + constant kINVERT_IQ_REGMask : std_logic_vector(31 downto 0) := X"0000ffff"; + constant kINVERT_DB0_ADC0_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC0_IQ + constant kINVERT_DB0_ADC0_IQMsb : integer := 0; --INVERT_IQ_REG:INVERT_DB0_ADC0_IQ + constant kINVERT_DB0_ADC0_IQ : integer := 0; --INVERT_IQ_REG:INVERT_DB0_ADC0_IQ + constant kINVERT_DB0_ADC1_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC1_IQ + constant kINVERT_DB0_ADC1_IQMsb : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC1_IQ + constant kINVERT_DB0_ADC1_IQ : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC1_IQ + constant kINVERT_DB0_ADC2_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC2_IQ + constant kINVERT_DB0_ADC2_IQMsb : integer := 2; --INVERT_IQ_REG:INVERT_DB0_ADC2_IQ + constant kINVERT_DB0_ADC2_IQ : integer := 2; --INVERT_IQ_REG:INVERT_DB0_ADC2_IQ + constant kINVERT_DB0_ADC3_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_ADC3_IQ + constant kINVERT_DB0_ADC3_IQMsb : integer := 3; --INVERT_IQ_REG:INVERT_DB0_ADC3_IQ + constant kINVERT_DB0_ADC3_IQ : integer := 3; --INVERT_IQ_REG:INVERT_DB0_ADC3_IQ + constant kINVERT_DB1_ADC0_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_ADC0_IQ + constant kINVERT_DB1_ADC0_IQMsb : integer := 4; --INVERT_IQ_REG:INVERT_DB1_ADC0_IQ + constant kINVERT_DB1_ADC0_IQ : integer := 4; --INVERT_IQ_REG:INVERT_DB1_ADC0_IQ + constant kINVERT_DB1_ADC1_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_ADC1_IQ + constant kINVERT_DB1_ADC1_IQMsb : integer := 5; --INVERT_IQ_REG:INVERT_DB1_ADC1_IQ + constant kINVERT_DB1_ADC1_IQ : integer := 5; --INVERT_IQ_REG:INVERT_DB1_ADC1_IQ + constant kINVERT_DB1_ADC2_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_ADC2_IQ + constant kINVERT_DB1_ADC2_IQMsb : integer := 6; --INVERT_IQ_REG:INVERT_DB1_ADC2_IQ + constant kINVERT_DB1_ADC2_IQ : integer := 6; --INVERT_IQ_REG:INVERT_DB1_ADC2_IQ + constant kINVERT_DB1_ADC3_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_ADC3_IQ + constant kINVERT_DB1_ADC3_IQMsb : integer := 7; --INVERT_IQ_REG:INVERT_DB1_ADC3_IQ + constant kINVERT_DB1_ADC3_IQ : integer := 7; --INVERT_IQ_REG:INVERT_DB1_ADC3_IQ + constant kINVERT_DB0_DAC0_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_DAC0_IQ + constant kINVERT_DB0_DAC0_IQMsb : integer := 8; --INVERT_IQ_REG:INVERT_DB0_DAC0_IQ + constant kINVERT_DB0_DAC0_IQ : integer := 8; --INVERT_IQ_REG:INVERT_DB0_DAC0_IQ + constant kINVERT_DB0_DAC1_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_DAC1_IQ + constant kINVERT_DB0_DAC1_IQMsb : integer := 9; --INVERT_IQ_REG:INVERT_DB0_DAC1_IQ + constant kINVERT_DB0_DAC1_IQ : integer := 9; --INVERT_IQ_REG:INVERT_DB0_DAC1_IQ + constant kINVERT_DB0_DAC2_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_DAC2_IQ + constant kINVERT_DB0_DAC2_IQMsb : integer := 10; --INVERT_IQ_REG:INVERT_DB0_DAC2_IQ + constant kINVERT_DB0_DAC2_IQ : integer := 10; --INVERT_IQ_REG:INVERT_DB0_DAC2_IQ + constant kINVERT_DB0_DAC3_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB0_DAC3_IQ + constant kINVERT_DB0_DAC3_IQMsb : integer := 11; --INVERT_IQ_REG:INVERT_DB0_DAC3_IQ + constant kINVERT_DB0_DAC3_IQ : integer := 11; --INVERT_IQ_REG:INVERT_DB0_DAC3_IQ + constant kINVERT_DB1_DAC0_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_DAC0_IQ + constant kINVERT_DB1_DAC0_IQMsb : integer := 12; --INVERT_IQ_REG:INVERT_DB1_DAC0_IQ + constant kINVERT_DB1_DAC0_IQ : integer := 12; --INVERT_IQ_REG:INVERT_DB1_DAC0_IQ + constant kINVERT_DB1_DAC1_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_DAC1_IQ + constant kINVERT_DB1_DAC1_IQMsb : integer := 13; --INVERT_IQ_REG:INVERT_DB1_DAC1_IQ + constant kINVERT_DB1_DAC1_IQ : integer := 13; --INVERT_IQ_REG:INVERT_DB1_DAC1_IQ + constant kINVERT_DB1_DAC2_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_DAC2_IQ + constant kINVERT_DB1_DAC2_IQMsb : integer := 14; --INVERT_IQ_REG:INVERT_DB1_DAC2_IQ + constant kINVERT_DB1_DAC2_IQ : integer := 14; --INVERT_IQ_REG:INVERT_DB1_DAC2_IQ + constant kINVERT_DB1_DAC3_IQSize : integer := 1; --INVERT_IQ_REG:INVERT_DB1_DAC3_IQ + constant kINVERT_DB1_DAC3_IQMsb : integer := 15; --INVERT_IQ_REG:INVERT_DB1_DAC3_IQ + constant kINVERT_DB1_DAC3_IQ : integer := 15; --INVERT_IQ_REG:INVERT_DB1_DAC3_IQ + --function kINVERT_IQ_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- MMCM_RESET_REG Register (from common_regs.v) + constant kMMCM_RESET_REG : integer := 16#11000#; -- Register Offset + constant kMMCM_RESET_REGSize: integer := 32; -- register width in bits + constant kMMCM_RESET_REGMask : std_logic_vector(31 downto 0) := X"00000001"; + constant kRESET_MMCMSize : integer := 1; --MMCM_RESET_REG:RESET_MMCM + constant kRESET_MMCMMsb : integer := 0; --MMCM_RESET_REG:RESET_MMCM + constant kRESET_MMCM : integer := 0; --MMCM_RESET_REG:RESET_MMCM + --function kMMCM_RESET_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RF_RESET_CONTROL_REG Register (from common_regs.v) + constant kRF_RESET_CONTROL_REG : integer := 16#12000#; -- Register Offset + constant kRF_RESET_CONTROL_REGSize: integer := 32; -- register width in bits + constant kRF_RESET_CONTROL_REGMask : std_logic_vector(31 downto 0) := X"00000331"; + constant kFSM_RESETSize : integer := 1; --RF_RESET_CONTROL_REG:FSM_RESET + constant kFSM_RESETMsb : integer := 0; --RF_RESET_CONTROL_REG:FSM_RESET + constant kFSM_RESET : integer := 0; --RF_RESET_CONTROL_REG:FSM_RESET + constant kADC_RESETSize : integer := 1; --RF_RESET_CONTROL_REG:ADC_RESET + constant kADC_RESETMsb : integer := 4; --RF_RESET_CONTROL_REG:ADC_RESET + constant kADC_RESET : integer := 4; --RF_RESET_CONTROL_REG:ADC_RESET + constant kADC_ENABLESize : integer := 1; --RF_RESET_CONTROL_REG:ADC_ENABLE + constant kADC_ENABLEMsb : integer := 5; --RF_RESET_CONTROL_REG:ADC_ENABLE + constant kADC_ENABLE : integer := 5; --RF_RESET_CONTROL_REG:ADC_ENABLE + constant kDAC_RESETSize : integer := 1; --RF_RESET_CONTROL_REG:DAC_RESET + constant kDAC_RESETMsb : integer := 8; --RF_RESET_CONTROL_REG:DAC_RESET + constant kDAC_RESET : integer := 8; --RF_RESET_CONTROL_REG:DAC_RESET + constant kDAC_ENABLESize : integer := 1; --RF_RESET_CONTROL_REG:DAC_ENABLE + constant kDAC_ENABLEMsb : integer := 9; --RF_RESET_CONTROL_REG:DAC_ENABLE + constant kDAC_ENABLE : integer := 9; --RF_RESET_CONTROL_REG:DAC_ENABLE + --function kRF_RESET_CONTROL_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RF_RESET_STATUS_REG Register (from common_regs.v) + constant kRF_RESET_STATUS_REG : integer := 16#12008#; -- Register Offset + constant kRF_RESET_STATUS_REGSize: integer := 32; -- register width in bits + constant kRF_RESET_STATUS_REGMask : std_logic_vector(31 downto 0) := X"00000888"; + constant kFSM_RESET_DONESize : integer := 1; --RF_RESET_STATUS_REG:FSM_RESET_DONE + constant kFSM_RESET_DONEMsb : integer := 3; --RF_RESET_STATUS_REG:FSM_RESET_DONE + constant kFSM_RESET_DONE : integer := 3; --RF_RESET_STATUS_REG:FSM_RESET_DONE + constant kADC_SEQ_DONESize : integer := 1; --RF_RESET_STATUS_REG:ADC_SEQ_DONE + constant kADC_SEQ_DONEMsb : integer := 7; --RF_RESET_STATUS_REG:ADC_SEQ_DONE + constant kADC_SEQ_DONE : integer := 7; --RF_RESET_STATUS_REG:ADC_SEQ_DONE + constant kDAC_SEQ_DONESize : integer := 1; --RF_RESET_STATUS_REG:DAC_SEQ_DONE + constant kDAC_SEQ_DONEMsb : integer := 11; --RF_RESET_STATUS_REG:DAC_SEQ_DONE + constant kDAC_SEQ_DONE : integer := 11; --RF_RESET_STATUS_REG:DAC_SEQ_DONE + --function kRF_RESET_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RF_AXI_STATUS_REG Register (from common_regs.v) + constant kRF_AXI_STATUS_REG : integer := 16#13000#; -- Register Offset + constant kRF_AXI_STATUS_REGSize: integer := 32; -- register width in bits + constant kRF_AXI_STATUS_REGMask : std_logic_vector(31 downto 0) := X"ffffffff"; + constant kRFDC_DAC_TREADYSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY + constant kRFDC_DAC_TREADYMsb : integer := 1; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY + constant kRFDC_DAC_TREADY : integer := 0; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY + constant kRFDC_DAC_TVALIDSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID + constant kRFDC_DAC_TVALIDMsb : integer := 3; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID + constant kRFDC_DAC_TVALID : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID + constant kRFDC_ADC_Q_TREADYSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY + constant kRFDC_ADC_Q_TREADYMsb : integer := 5; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY + constant kRFDC_ADC_Q_TREADY : integer := 4; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY + constant kRFDC_ADC_I_TREADYSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY + constant kRFDC_ADC_I_TREADYMsb : integer := 7; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY + constant kRFDC_ADC_I_TREADY : integer := 6; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY + constant kRFDC_ADC_Q_TVALIDSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID + constant kRFDC_ADC_Q_TVALIDMsb : integer := 9; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID + constant kRFDC_ADC_Q_TVALID : integer := 8; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID + constant kRFDC_ADC_I_TVALIDSize : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID + constant kRFDC_ADC_I_TVALIDMsb : integer := 11; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID + constant kRFDC_ADC_I_TVALID : integer := 10; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID + constant kUSER_ADC_TVALIDSize : integer := 2; --RF_AXI_STATUS_REG:USER_ADC_TVALID + constant kUSER_ADC_TVALIDMsb : integer := 13; --RF_AXI_STATUS_REG:USER_ADC_TVALID + constant kUSER_ADC_TVALID : integer := 12; --RF_AXI_STATUS_REG:USER_ADC_TVALID + constant kUSER_ADC_TREADYSize : integer := 2; --RF_AXI_STATUS_REG:USER_ADC_TREADY + constant kUSER_ADC_TREADYMsb : integer := 15; --RF_AXI_STATUS_REG:USER_ADC_TREADY + constant kUSER_ADC_TREADY : integer := 14; --RF_AXI_STATUS_REG:USER_ADC_TREADY + constant kRFDC_DAC_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1 + constant kRFDC_DAC_TREADY_DB1Msb : integer := 17; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1 + constant kRFDC_DAC_TREADY_DB1 : integer := 16; --RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1 + constant kRFDC_DAC_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1 + constant kRFDC_DAC_TVALID_DB1Msb : integer := 19; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1 + constant kRFDC_DAC_TVALID_DB1 : integer := 18; --RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1 + constant kRFDC_ADC_Q_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1 + constant kRFDC_ADC_Q_TREADY_DB1Msb : integer := 21; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1 + constant kRFDC_ADC_Q_TREADY_DB1 : integer := 20; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1 + constant kRFDC_ADC_I_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1 + constant kRFDC_ADC_I_TREADY_DB1Msb : integer := 23; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1 + constant kRFDC_ADC_I_TREADY_DB1 : integer := 22; --RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1 + constant kRFDC_ADC_Q_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1 + constant kRFDC_ADC_Q_TVALID_DB1Msb : integer := 25; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1 + constant kRFDC_ADC_Q_TVALID_DB1 : integer := 24; --RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1 + constant kRFDC_ADC_I_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1 + constant kRFDC_ADC_I_TVALID_DB1Msb : integer := 27; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1 + constant kRFDC_ADC_I_TVALID_DB1 : integer := 26; --RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1 + constant kUSER_ADC_TVALID_DB1Size : integer := 2; --RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1 + constant kUSER_ADC_TVALID_DB1Msb : integer := 29; --RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1 + constant kUSER_ADC_TVALID_DB1 : integer := 28; --RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1 + constant kUSER_ADC_TREADY_DB1Size : integer := 2; --RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1 + constant kUSER_ADC_TREADY_DB1Msb : integer := 31; --RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1 + constant kUSER_ADC_TREADY_DB1 : integer := 30; --RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1 + --function kRF_AXI_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- FABRIC_DSP_REG Register (from common_regs.v) + constant kFABRIC_DSP_REG : integer := 16#13008#; -- Register Offset + constant kFABRIC_DSP_REGSize: integer := 32; -- register width in bits + constant kFABRIC_DSP_REGMask : std_logic_vector(31 downto 0) := X"ffffffff"; + constant kFABRIC_DSP_BWSize : integer := 12; --FABRIC_DSP_REG:FABRIC_DSP_BW + constant kFABRIC_DSP_BWMsb : integer := 11; --FABRIC_DSP_REG:FABRIC_DSP_BW + constant kFABRIC_DSP_BW : integer := 0; --FABRIC_DSP_REG:FABRIC_DSP_BW + constant kFABRIC_DSP_RX_CNTSize : integer := 2; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT + constant kFABRIC_DSP_RX_CNTMsb : integer := 13; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT + constant kFABRIC_DSP_RX_CNT : integer := 12; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT + constant kFABRIC_DSP_TX_CNTSize : integer := 2; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT + constant kFABRIC_DSP_TX_CNTMsb : integer := 15; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT + constant kFABRIC_DSP_TX_CNT : integer := 14; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT + constant kFABRIC_DSP_BW_DB1Size : integer := 12; --FABRIC_DSP_REG:FABRIC_DSP_BW_DB1 + constant kFABRIC_DSP_BW_DB1Msb : integer := 27; --FABRIC_DSP_REG:FABRIC_DSP_BW_DB1 + constant kFABRIC_DSP_BW_DB1 : integer := 16; --FABRIC_DSP_REG:FABRIC_DSP_BW_DB1 + constant kFABRIC_DSP_RX_CNT_DB1Size : integer := 2; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1 + constant kFABRIC_DSP_RX_CNT_DB1Msb : integer := 29; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1 + constant kFABRIC_DSP_RX_CNT_DB1 : integer := 28; --FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1 + constant kFABRIC_DSP_TX_CNT_DB1Size : integer := 2; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1 + constant kFABRIC_DSP_TX_CNT_DB1Msb : integer := 31; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1 + constant kFABRIC_DSP_TX_CNT_DB1 : integer := 30; --FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1 + --function kFABRIC_DSP_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- CALIBRATION_DATA Register (from common_regs.v) + constant kCALIBRATION_DATA : integer := 16#14000#; -- Register Offset + constant kCALIBRATION_DATASize: integer := 32; -- register width in bits + constant kCALIBRATION_DATAMask : std_logic_vector(31 downto 0) := X"ffffffff"; + constant kI_DATASize : integer := 16; --CALIBRATION_DATA:I_DATA + constant kI_DATAMsb : integer := 15; --CALIBRATION_DATA:I_DATA + constant kI_DATA : integer := 0; --CALIBRATION_DATA:I_DATA + constant kQ_DATASize : integer := 16; --CALIBRATION_DATA:Q_DATA + constant kQ_DATAMsb : integer := 31; --CALIBRATION_DATA:Q_DATA + constant kQ_DATA : integer := 16; --CALIBRATION_DATA:Q_DATA + --function kCALIBRATION_DATARec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- CALIBRATION_ENABLE Register (from common_regs.v) + constant kCALIBRATION_ENABLE : integer := 16#14008#; -- Register Offset + constant kCALIBRATION_ENABLESize: integer := 32; -- register width in bits + constant kCALIBRATION_ENABLEMask : std_logic_vector(31 downto 0) := X"00000033"; + constant kENABLE_CALIBRATION_DATA_0Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 + constant kENABLE_CALIBRATION_DATA_0Msb : integer := 0; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 + constant kENABLE_CALIBRATION_DATA_0 : integer := 0; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 + constant kENABLE_CALIBRATION_DATA_1Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 + constant kENABLE_CALIBRATION_DATA_1Msb : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 + constant kENABLE_CALIBRATION_DATA_1 : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 + constant kENABLE_CALIBRATION_DATA_2Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 + constant kENABLE_CALIBRATION_DATA_2Msb : integer := 4; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 + constant kENABLE_CALIBRATION_DATA_2 : integer := 4; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 + constant kENABLE_CALIBRATION_DATA_3Size : integer := 1; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 + constant kENABLE_CALIBRATION_DATA_3Msb : integer := 5; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 + constant kENABLE_CALIBRATION_DATA_3 : integer := 5; --CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 + --function kCALIBRATION_ENABLERec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- THRESHOLD_STATUS Register (from common_regs.v) + constant kTHRESHOLD_STATUS : integer := 16#15000#; -- Register Offset + constant kTHRESHOLD_STATUSSize: integer := 32; -- register width in bits + constant kTHRESHOLD_STATUSMask : std_logic_vector(31 downto 0) := X"00000f0f"; + constant kADC0_01_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD1 + constant kADC0_01_THRESHOLD1Msb : integer := 0; --THRESHOLD_STATUS:ADC0_01_THRESHOLD1 + constant kADC0_01_THRESHOLD1 : integer := 0; --THRESHOLD_STATUS:ADC0_01_THRESHOLD1 + constant kADC0_01_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD2 + constant kADC0_01_THRESHOLD2Msb : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD2 + constant kADC0_01_THRESHOLD2 : integer := 1; --THRESHOLD_STATUS:ADC0_01_THRESHOLD2 + constant kADC0_23_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC0_23_THRESHOLD1 + constant kADC0_23_THRESHOLD1Msb : integer := 2; --THRESHOLD_STATUS:ADC0_23_THRESHOLD1 + constant kADC0_23_THRESHOLD1 : integer := 2; --THRESHOLD_STATUS:ADC0_23_THRESHOLD1 + constant kADC0_23_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC0_23_THRESHOLD2 + constant kADC0_23_THRESHOLD2Msb : integer := 3; --THRESHOLD_STATUS:ADC0_23_THRESHOLD2 + constant kADC0_23_THRESHOLD2 : integer := 3; --THRESHOLD_STATUS:ADC0_23_THRESHOLD2 + constant kADC2_01_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC2_01_THRESHOLD1 + constant kADC2_01_THRESHOLD1Msb : integer := 8; --THRESHOLD_STATUS:ADC2_01_THRESHOLD1 + constant kADC2_01_THRESHOLD1 : integer := 8; --THRESHOLD_STATUS:ADC2_01_THRESHOLD1 + constant kADC2_01_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC2_01_THRESHOLD2 + constant kADC2_01_THRESHOLD2Msb : integer := 9; --THRESHOLD_STATUS:ADC2_01_THRESHOLD2 + constant kADC2_01_THRESHOLD2 : integer := 9; --THRESHOLD_STATUS:ADC2_01_THRESHOLD2 + constant kADC2_23_THRESHOLD1Size : integer := 1; --THRESHOLD_STATUS:ADC2_23_THRESHOLD1 + constant kADC2_23_THRESHOLD1Msb : integer := 10; --THRESHOLD_STATUS:ADC2_23_THRESHOLD1 + constant kADC2_23_THRESHOLD1 : integer := 10; --THRESHOLD_STATUS:ADC2_23_THRESHOLD1 + constant kADC2_23_THRESHOLD2Size : integer := 1; --THRESHOLD_STATUS:ADC2_23_THRESHOLD2 + constant kADC2_23_THRESHOLD2Msb : integer := 11; --THRESHOLD_STATUS:ADC2_23_THRESHOLD2 + constant kADC2_23_THRESHOLD2 : integer := 11; --THRESHOLD_STATUS:ADC2_23_THRESHOLD2 + --function kTHRESHOLD_STATUSRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RF_PLL_CONTROL_REG Register (from common_regs.v) + constant kRF_PLL_CONTROL_REG : integer := 16#16000#; -- Register Offset + constant kRF_PLL_CONTROL_REGSize: integer := 32; -- register width in bits + constant kRF_PLL_CONTROL_REGMask : std_logic_vector(31 downto 0) := X"00011111"; + constant kENABLE_DATA_CLKSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK + constant kENABLE_DATA_CLKMsb : integer := 0; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK + constant kENABLE_DATA_CLK : integer := 0; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK + constant kENABLE_DATA_CLK_2XSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X + constant kENABLE_DATA_CLK_2XMsb : integer := 4; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X + constant kENABLE_DATA_CLK_2X : integer := 4; --RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X + constant kENABLE_RF_CLKSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK + constant kENABLE_RF_CLKMsb : integer := 8; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK + constant kENABLE_RF_CLK : integer := 8; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK + constant kENABLE_RF_CLK_2XSize : integer := 1; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X + constant kENABLE_RF_CLK_2XMsb : integer := 12; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X + constant kENABLE_RF_CLK_2X : integer := 12; --RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X + constant kCLEAR_DATA_CLK_UNLOCKEDSize : integer := 1; --RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED + constant kCLEAR_DATA_CLK_UNLOCKEDMsb : integer := 16; --RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED + constant kCLEAR_DATA_CLK_UNLOCKED : integer := 16; --RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED + --function kRF_PLL_CONTROL_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + + -- RF_PLL_STATUS_REG Register (from common_regs.v) + constant kRF_PLL_STATUS_REG : integer := 16#16008#; -- Register Offset + constant kRF_PLL_STATUS_REGSize: integer := 32; -- register width in bits + constant kRF_PLL_STATUS_REGMask : std_logic_vector(31 downto 0) := X"00110000"; + constant kDATA_CLK_PLL_UNLOCKED_STICKYSize : integer := 1; --RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY + constant kDATA_CLK_PLL_UNLOCKED_STICKYMsb : integer := 16; --RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY + constant kDATA_CLK_PLL_UNLOCKED_STICKY : integer := 16; --RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY + constant kDATA_CLK_PLL_LOCKEDSize : integer := 1; --RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED + constant kDATA_CLK_PLL_LOCKEDMsb : integer := 20; --RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED + constant kDATA_CLK_PLL_LOCKED : integer := 20; --RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED + --function kRF_PLL_STATUS_REGRec return XReg2_t; -- Register Record function commented out due to programmable attributes + +end package; + +package body PkgRFDC_REGS_REGMAP is + + -- function kMMCMRec not implemented because MMCM has programmable attributes + ---- Return the record of window kMMCM + --function kMMCMRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"0"); + -- Rec.size := kMMCMSize; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"00"); + -- Rec.rmask := XRegResize(X"00"); + -- Rec.strobemask := XRegResize(X"00"); + -- Rec.clearablemask := XRegResize(X"00"); + -- Rec.iswin := true; + -- --synopsys translate_off + -- Rec.name := rs("MMCM"); + -- --synopsys translate_on + -- return Rec; + --end function kMMCMRec; + + -- function kINVERT_IQ_REGRec not implemented because INVERT_IQ_REG has programmable attributes + ---- Return the record of register kINVERT_IQ_REG + --function kINVERT_IQ_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"10000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"0000ffff"); + -- Rec.rmask := XRegResize(X"0000ffff"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("INVERT_IQ_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kINVERT_IQ_REGRec; + + -- function kMMCM_RESET_REGRec not implemented because MMCM_RESET_REG has programmable attributes + ---- Return the record of register kMMCM_RESET_REG + --function kMMCM_RESET_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"11000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"00000001"); + -- Rec.rmask := XRegResize(X"00000001"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("MMCM_RESET_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kMMCM_RESET_REGRec; + + -- function kRF_RESET_CONTROL_REGRec not implemented because RF_RESET_CONTROL_REG has programmable attributes + ---- Return the record of register kRF_RESET_CONTROL_REG + --function kRF_RESET_CONTROL_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"12000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"00000331"); + -- Rec.rmask := XRegResize(X"00000331"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RF_RESET_CONTROL_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRF_RESET_CONTROL_REGRec; + + -- function kRF_RESET_STATUS_REGRec not implemented because RF_RESET_STATUS_REG has programmable attributes + ---- Return the record of register kRF_RESET_STATUS_REG + --function kRF_RESET_STATUS_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"12008"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := false; + -- Rec.wmask := XRegResize(X"00000888"); + -- Rec.rmask := XRegResize(X"00000888"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RF_RESET_STATUS_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRF_RESET_STATUS_REGRec; + + -- function kRF_AXI_STATUS_REGRec not implemented because RF_AXI_STATUS_REG has programmable attributes + ---- Return the record of register kRF_AXI_STATUS_REG + --function kRF_AXI_STATUS_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"13000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := false; + -- Rec.wmask := XRegResize(X"ffffffff"); + -- Rec.rmask := XRegResize(X"ffffffff"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.msblookupw(kRFDC_DAC_TREADY) := kRFDC_DAC_TREADYMsb; + -- Rec.msblookupw(kRFDC_DAC_TVALID) := kRFDC_DAC_TVALIDMsb; + -- Rec.msblookupw(kRFDC_ADC_Q_TREADY) := kRFDC_ADC_Q_TREADYMsb; + -- Rec.msblookupw(kRFDC_ADC_I_TREADY) := kRFDC_ADC_I_TREADYMsb; + -- Rec.msblookupw(kRFDC_ADC_Q_TVALID) := kRFDC_ADC_Q_TVALIDMsb; + -- Rec.msblookupw(kRFDC_ADC_I_TVALID) := kRFDC_ADC_I_TVALIDMsb; + -- Rec.msblookupw(kUSER_ADC_TVALID) := kUSER_ADC_TVALIDMsb; + -- Rec.msblookupw(kUSER_ADC_TREADY) := kUSER_ADC_TREADYMsb; + -- Rec.msblookupw(kRFDC_DAC_TREADY_DB1) := kRFDC_DAC_TREADY_DB1Msb; + -- Rec.msblookupw(kRFDC_DAC_TVALID_DB1) := kRFDC_DAC_TVALID_DB1Msb; + -- Rec.msblookupw(kRFDC_ADC_Q_TREADY_DB1) := kRFDC_ADC_Q_TREADY_DB1Msb; + -- Rec.msblookupw(kRFDC_ADC_I_TREADY_DB1) := kRFDC_ADC_I_TREADY_DB1Msb; + -- Rec.msblookupw(kRFDC_ADC_Q_TVALID_DB1) := kRFDC_ADC_Q_TVALID_DB1Msb; + -- Rec.msblookupw(kRFDC_ADC_I_TVALID_DB1) := kRFDC_ADC_I_TVALID_DB1Msb; + -- Rec.msblookupw(kUSER_ADC_TVALID_DB1) := kUSER_ADC_TVALID_DB1Msb; + -- Rec.msblookupw(kUSER_ADC_TREADY_DB1) := kUSER_ADC_TREADY_DB1Msb; + -- Rec.msblookupr(kRFDC_DAC_TREADY) := kRFDC_DAC_TREADYMsb; + -- Rec.msblookupr(kRFDC_DAC_TVALID) := kRFDC_DAC_TVALIDMsb; + -- Rec.msblookupr(kRFDC_ADC_Q_TREADY) := kRFDC_ADC_Q_TREADYMsb; + -- Rec.msblookupr(kRFDC_ADC_I_TREADY) := kRFDC_ADC_I_TREADYMsb; + -- Rec.msblookupr(kRFDC_ADC_Q_TVALID) := kRFDC_ADC_Q_TVALIDMsb; + -- Rec.msblookupr(kRFDC_ADC_I_TVALID) := kRFDC_ADC_I_TVALIDMsb; + -- Rec.msblookupr(kUSER_ADC_TVALID) := kUSER_ADC_TVALIDMsb; + -- Rec.msblookupr(kUSER_ADC_TREADY) := kUSER_ADC_TREADYMsb; + -- Rec.msblookupr(kRFDC_DAC_TREADY_DB1) := kRFDC_DAC_TREADY_DB1Msb; + -- Rec.msblookupr(kRFDC_DAC_TVALID_DB1) := kRFDC_DAC_TVALID_DB1Msb; + -- Rec.msblookupr(kRFDC_ADC_Q_TREADY_DB1) := kRFDC_ADC_Q_TREADY_DB1Msb; + -- Rec.msblookupr(kRFDC_ADC_I_TREADY_DB1) := kRFDC_ADC_I_TREADY_DB1Msb; + -- Rec.msblookupr(kRFDC_ADC_Q_TVALID_DB1) := kRFDC_ADC_Q_TVALID_DB1Msb; + -- Rec.msblookupr(kRFDC_ADC_I_TVALID_DB1) := kRFDC_ADC_I_TVALID_DB1Msb; + -- Rec.msblookupr(kUSER_ADC_TVALID_DB1) := kUSER_ADC_TVALID_DB1Msb; + -- Rec.msblookupr(kUSER_ADC_TREADY_DB1) := kUSER_ADC_TREADY_DB1Msb; + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RF_AXI_STATUS_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRF_AXI_STATUS_REGRec; + + -- function kFABRIC_DSP_REGRec not implemented because FABRIC_DSP_REG has programmable attributes + ---- Return the record of register kFABRIC_DSP_REG + --function kFABRIC_DSP_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"13008"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := false; + -- Rec.wmask := XRegResize(X"ffffffff"); + -- Rec.rmask := XRegResize(X"ffffffff"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- Rec.initialvalue := XRegResize(X"00000000"); + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.msblookupw(kFABRIC_DSP_BW) := kFABRIC_DSP_BWMsb; + -- Rec.msblookupw(kFABRIC_DSP_RX_CNT) := kFABRIC_DSP_RX_CNTMsb; + -- Rec.msblookupw(kFABRIC_DSP_TX_CNT) := kFABRIC_DSP_TX_CNTMsb; + -- Rec.msblookupw(kFABRIC_DSP_BW_DB1) := kFABRIC_DSP_BW_DB1Msb; + -- Rec.msblookupw(kFABRIC_DSP_RX_CNT_DB1) := kFABRIC_DSP_RX_CNT_DB1Msb; + -- Rec.msblookupw(kFABRIC_DSP_TX_CNT_DB1) := kFABRIC_DSP_TX_CNT_DB1Msb; + -- Rec.msblookupr(kFABRIC_DSP_BW) := kFABRIC_DSP_BWMsb; + -- Rec.msblookupr(kFABRIC_DSP_RX_CNT) := kFABRIC_DSP_RX_CNTMsb; + -- Rec.msblookupr(kFABRIC_DSP_TX_CNT) := kFABRIC_DSP_TX_CNTMsb; + -- Rec.msblookupr(kFABRIC_DSP_BW_DB1) := kFABRIC_DSP_BW_DB1Msb; + -- Rec.msblookupr(kFABRIC_DSP_RX_CNT_DB1) := kFABRIC_DSP_RX_CNT_DB1Msb; + -- Rec.msblookupr(kFABRIC_DSP_TX_CNT_DB1) := kFABRIC_DSP_TX_CNT_DB1Msb; + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("FABRIC_DSP_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kFABRIC_DSP_REGRec; + + -- function kCALIBRATION_DATARec not implemented because CALIBRATION_DATA has programmable attributes + ---- Return the record of register kCALIBRATION_DATA + --function kCALIBRATION_DATARec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"14000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"ffffffff"); + -- Rec.rmask := XRegResize(X"ffffffff"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.msblookupw(kI_DATA) := kI_DATAMsb; + -- Rec.msblookupw(kQ_DATA) := kQ_DATAMsb; + -- Rec.msblookupr(kI_DATA) := kI_DATAMsb; + -- Rec.msblookupr(kQ_DATA) := kQ_DATAMsb; + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("CALIBRATION_DATA"); + -- --synopsys translate_on + -- return Rec; + --end function kCALIBRATION_DATARec; + + -- function kCALIBRATION_ENABLERec not implemented because CALIBRATION_ENABLE has programmable attributes + ---- Return the record of register kCALIBRATION_ENABLE + --function kCALIBRATION_ENABLERec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"14008"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"00000033"); + -- Rec.rmask := XRegResize(X"00000033"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("CALIBRATION_ENABLE"); + -- --synopsys translate_on + -- return Rec; + --end function kCALIBRATION_ENABLERec; + + -- function kTHRESHOLD_STATUSRec not implemented because THRESHOLD_STATUS has programmable attributes + ---- Return the record of register kTHRESHOLD_STATUS + --function kTHRESHOLD_STATUSRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"15000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"00000f0f"); + -- Rec.rmask := XRegResize(X"00000f0f"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("THRESHOLD_STATUS"); + -- --synopsys translate_on + -- return Rec; + --end function kTHRESHOLD_STATUSRec; + + -- function kRF_PLL_CONTROL_REGRec not implemented because RF_PLL_CONTROL_REG has programmable attributes + ---- Return the record of register kRF_PLL_CONTROL_REG + --function kRF_PLL_CONTROL_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"16000"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := true; + -- Rec.wmask := XRegResize(X"00011111"); + -- Rec.rmask := XRegResize(X"00011111"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RF_PLL_CONTROL_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRF_PLL_CONTROL_REGRec; + + -- function kRF_PLL_STATUS_REGRec not implemented because RF_PLL_STATUS_REG has programmable attributes + ---- Return the record of register kRF_PLL_STATUS_REG + --function kRF_PLL_STATUS_REGRec return XReg2_t is + -- variable Rec : XReg2_t; + --begin + -- Rec := kXRegDefault; + -- Rec.version := 1; + -- Rec.offset := XAddrResize(X"16008"); + -- Rec.size := 32; + -- Rec.readable := true; + -- Rec.writable := false; + -- Rec.wmask := XRegResize(X"00110000"); + -- Rec.rmask := XRegResize(X"00110000"); + -- Rec.strobemask := XRegResize(X"00000000"); + -- Rec.clearablemask := XRegResize(X"00000000"); + -- -- no initial values specified + -- -- Single-bit bitfields are not listed here because the default for msblookup* is msb=lsb. + -- Rec.isreg := true; + -- --synopsys translate_off + -- Rec.name := rs("RF_PLL_STATUS_REG"); + -- --synopsys translate_on + -- return Rec; + --end function kRF_PLL_STATUS_REGRec; + +end package body; diff --git a/fpga/usrp3/top/x400/regmap/axi_hpm0_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/axi_hpm0_regmap_utils.vh new file mode 100644 index 000000000..a493bafc3 --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/axi_hpm0_regmap_utils.vh @@ -0,0 +1,110 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: axi_hpm0_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // RPU : 0x80000000 (common_regs.v) + // JTAG_ENGINE : 0x1000000000 (common_regs.v) + // WR : 0x100003F000 (common_regs.v) + // MPM_ENDPOINT : 0x1000080000 (common_regs.v) + // CORE_REGS : 0x10000A0000 (common_regs.v) + // INT_ETH_DMA : 0x10000A4000 (common_regs.v) + // INT_ETH_REGS : 0x10000AA000 (common_regs.v) + // RFDC : 0x1000100000 (common_regs.v) + // RFDC_REGS : 0x1000140000 (common_regs.v) + // QSFP_0_0 : 0x1200000000 (uhd_regs.v) + // QSFP_0_1 : 0x1200010000 (uhd_regs.v) + // QSFP_0_2 : 0x1200020000 (uhd_regs.v) + // QSFP_0_3 : 0x1200030000 (uhd_regs.v) + // QSFP_1_0 : 0x1200040000 (uhd_regs.v) + // QSFP_1_1 : 0x1200050000 (uhd_regs.v) + // QSFP_1_2 : 0x1200060000 (uhd_regs.v) + // QSFP_1_3 : 0x1200070000 (uhd_regs.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group COMMON +//=============================================================================== + + // RPU Window (from common_regs.v) + localparam RPU = 'h80000000; // Window Offset + localparam RPU_SIZE = 'h10000; // size in bytes + + // JTAG_ENGINE Window (from common_regs.v) + localparam JTAG_ENGINE = 'h1000000000; // Window Offset + localparam JTAG_ENGINE_SIZE = 'h1000; // size in bytes + + // WR Window (from common_regs.v) + localparam WR = 'h100003F000; // Window Offset + localparam WR_SIZE = 'h1000; // size in bytes + + // MPM_ENDPOINT Window (from common_regs.v) + localparam MPM_ENDPOINT = 'h1000080000; // Window Offset + localparam MPM_ENDPOINT_SIZE = 'h20000; // size in bytes + + // CORE_REGS Window (from common_regs.v) + localparam CORE_REGS = 'h10000A0000; // Window Offset + localparam CORE_REGS_SIZE = 'h4000; // size in bytes + + // INT_ETH_DMA Window (from common_regs.v) + localparam INT_ETH_DMA = 'h10000A4000; // Window Offset + localparam INT_ETH_DMA_SIZE = 'h6000; // size in bytes + + // INT_ETH_REGS Window (from common_regs.v) + localparam INT_ETH_REGS = 'h10000AA000; // Window Offset + localparam INT_ETH_REGS_SIZE = 'h2000; // size in bytes + + // RFDC Window (from common_regs.v) + localparam RFDC = 'h1000100000; // Window Offset + localparam RFDC_SIZE = 'h40000; // size in bytes + + // RFDC_REGS Window (from common_regs.v) + localparam RFDC_REGS = 'h1000140000; // Window Offset + localparam RFDC_REGS_SIZE = 'h20000; // size in bytes + +//=============================================================================== +// Register Group UHD_ONLY +//=============================================================================== + + // QSFP_0_0 Window (from uhd_regs.v) + localparam QSFP_0_0 = 'h1200000000; // Window Offset + localparam QSFP_0_0_SIZE = 'h10000; // size in bytes + + // QSFP_0_1 Window (from uhd_regs.v) + localparam QSFP_0_1 = 'h1200010000; // Window Offset + localparam QSFP_0_1_SIZE = 'h10000; // size in bytes + + // QSFP_0_2 Window (from uhd_regs.v) + localparam QSFP_0_2 = 'h1200020000; // Window Offset + localparam QSFP_0_2_SIZE = 'h10000; // size in bytes + + // QSFP_0_3 Window (from uhd_regs.v) + localparam QSFP_0_3 = 'h1200030000; // Window Offset + localparam QSFP_0_3_SIZE = 'h10000; // size in bytes + + // QSFP_1_0 Window (from uhd_regs.v) + localparam QSFP_1_0 = 'h1200040000; // Window Offset + localparam QSFP_1_0_SIZE = 'h10000; // size in bytes + + // QSFP_1_1 Window (from uhd_regs.v) + localparam QSFP_1_1 = 'h1200050000; // Window Offset + localparam QSFP_1_1_SIZE = 'h10000; // size in bytes + + // QSFP_1_2 Window (from uhd_regs.v) + localparam QSFP_1_2 = 'h1200060000; // Window Offset + localparam QSFP_1_2_SIZE = 'h10000; // size in bytes + + // QSFP_1_3 Window (from uhd_regs.v) + localparam QSFP_1_3 = 'h1200070000; // Window Offset + localparam QSFP_1_3_SIZE = 'h10000; // size in bytes diff --git a/fpga/usrp3/top/x400/regmap/core_regs_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/core_regs_regmap_utils.vh new file mode 100644 index 000000000..cef263b6d --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/core_regs_regmap_utils.vh @@ -0,0 +1,41 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: core_regs_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // GLOBAL_REGS : 0x0 (x4xx_core_common.v) + // VERSIONING_REGS : 0xC00 (x4xx_core_common.v) + // TIMEKEEPER : 0x1000 (x4xx_core_common.v) + // DIO : 0x2000 (x4xx_core_common.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group CORE_REGS +//=============================================================================== + + // GLOBAL_REGS Window (from x4xx_core_common.v) + localparam GLOBAL_REGS = 'h0; // Window Offset + localparam GLOBAL_REGS_SIZE = 'hC00; // size in bytes + + // VERSIONING_REGS Window (from x4xx_core_common.v) + localparam VERSIONING_REGS = 'hC00; // Window Offset + localparam VERSIONING_REGS_SIZE = 'h400; // size in byte + + // TIMEKEEPER Window (from x4xx_core_common.v) + localparam TIMEKEEPER = 'h1000; // Window Offset + localparam TIMEKEEPER_SIZE = 'h20; // size in bytes + + // DIO Window (from x4xx_core_common.v) + localparam DIO = 'h2000; // Window Offset + localparam DIO_SIZE = 'h20; // size in bytes diff --git a/fpga/usrp3/top/x400/regmap/cpld_interface_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/cpld_interface_regmap_utils.vh new file mode 100644 index 000000000..1539803fe --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/cpld_interface_regmap_utils.vh @@ -0,0 +1,71 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: cpld_interface_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // SIGNATURE_REGISTER : 0x0 (cpld_interface_regs.v) + // SCRATCH_REGISTER : 0xC (cpld_interface_regs.v) + // IPASS_CONTROL : 0x10 (cpld_interface_regs.v) + // MOTHERBOARD_CPLD_DIVIDER : 0x20 (cpld_interface_regs.v) + // DAUGHTERBOARD_CPLD_DIVIDER : 0x24 (cpld_interface_regs.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group CPLD_INTERFACE_REGS +//=============================================================================== + + // SIGNATURE_REGISTER Register (from cpld_interface_regs.v) + localparam SIGNATURE_REGISTER = 'h0; // Register Offset + localparam SIGNATURE_REGISTER_SIZE = 32; // register width in bits + localparam SIGNATURE_REGISTER_MASK = 32'hFFFFFFFF; + localparam PRODUCT_SIGNATURE_SIZE = 32; //SIGNATURE_REGISTER:PRODUCT_SIGNATURE + localparam PRODUCT_SIGNATURE_MSB = 31; //SIGNATURE_REGISTER:PRODUCT_SIGNATURE + localparam PRODUCT_SIGNATURE = 0; //SIGNATURE_REGISTER:PRODUCT_SIGNATURE + + // SCRATCH_REGISTER Register (from cpld_interface_regs.v) + localparam SCRATCH_REGISTER = 'hC; // Register Offset + localparam SCRATCH_REGISTER_SIZE = 32; // register width in bits + localparam SCRATCH_REGISTER_MASK = 32'h0; + +//=============================================================================== +// Register Group CPLD_SPI_CONTROL_REGS +//=============================================================================== + + // MOTHERBOARD_CPLD_DIVIDER Register (from cpld_interface_regs.v) + localparam MOTHERBOARD_CPLD_DIVIDER = 'h20; // Register Offset + localparam MOTHERBOARD_CPLD_DIVIDER_SIZE = 32; // register width in bits + localparam MOTHERBOARD_CPLD_DIVIDER_MASK = 32'hFFFF; + localparam MB_DIVIDER_SIZE = 16; //MOTHERBOARD_CPLD_DIVIDER:MB_DIVIDER + localparam MB_DIVIDER_MSB = 15; //MOTHERBOARD_CPLD_DIVIDER:MB_DIVIDER + localparam MB_DIVIDER = 0; //MOTHERBOARD_CPLD_DIVIDER:MB_DIVIDER + + // DAUGHTERBOARD_CPLD_DIVIDER Register (from cpld_interface_regs.v) + localparam DAUGHTERBOARD_CPLD_DIVIDER = 'h24; // Register Offset + localparam DAUGHTERBOARD_CPLD_DIVIDER_SIZE = 32; // register width in bits + localparam DAUGHTERBOARD_CPLD_DIVIDER_MASK = 32'hFFFF; + localparam DB_DIVIDER_SIZE = 16; //DAUGHTERBOARD_CPLD_DIVIDER:DB_DIVIDER + localparam DB_DIVIDER_MSB = 15; //DAUGHTERBOARD_CPLD_DIVIDER:DB_DIVIDER + localparam DB_DIVIDER = 0; //DAUGHTERBOARD_CPLD_DIVIDER:DB_DIVIDER + +//=============================================================================== +// Register Group IPASS_REGS +//=============================================================================== + + // IPASS_CONTROL Register (from cpld_interface_regs.v) + localparam IPASS_CONTROL = 'h10; // Register Offset + localparam IPASS_CONTROL_SIZE = 32; // register width in bits + localparam IPASS_CONTROL_MASK = 32'h1; + localparam IPASS_ENABLE_TRANSFER_SIZE = 1; //IPASS_CONTROL:IPASS_ENABLE_TRANSFER + localparam IPASS_ENABLE_TRANSFER_MSB = 0; //IPASS_CONTROL:IPASS_ENABLE_TRANSFER + localparam IPASS_ENABLE_TRANSFER = 0; //IPASS_CONTROL:IPASS_ENABLE_TRANSFER diff --git a/fpga/usrp3/top/x400/regmap/dio_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/dio_regmap_utils.vh new file mode 100644 index 000000000..7598bb1ee --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/dio_regmap_utils.vh @@ -0,0 +1,69 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: dio_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // DIO_MASTER_REGISTER : 0x0 (x4xx_dio.v) + // DIO_DIRECTION_REGISTER : 0x4 (x4xx_dio.v) + // DIO_INPUT_REGISTER : 0x8 (x4xx_dio.v) + // DIO_OUTPUT_REGISTER : 0xC (x4xx_dio.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group DIO_REGS +//=============================================================================== + + // DIO_MASTER_REGISTER Register (from x4xx_dio.v) + localparam DIO_MASTER_REGISTER = 'h0; // Register Offset + localparam DIO_MASTER_REGISTER_SIZE = 32; // register width in bits + localparam DIO_MASTER_REGISTER_MASK = 32'hFFF0FFF; + localparam DIO_MASTER_A_SIZE = 12; //DIO_MASTER_REGISTER:DIO_MASTER_A + localparam DIO_MASTER_A_MSB = 11; //DIO_MASTER_REGISTER:DIO_MASTER_A + localparam DIO_MASTER_A = 0; //DIO_MASTER_REGISTER:DIO_MASTER_A + localparam DIO_MASTER_B_SIZE = 12; //DIO_MASTER_REGISTER:DIO_MASTER_B + localparam DIO_MASTER_B_MSB = 27; //DIO_MASTER_REGISTER:DIO_MASTER_B + localparam DIO_MASTER_B = 16; //DIO_MASTER_REGISTER:DIO_MASTER_B + + // DIO_DIRECTION_REGISTER Register (from x4xx_dio.v) + localparam DIO_DIRECTION_REGISTER = 'h4; // Register Offset + localparam DIO_DIRECTION_REGISTER_SIZE = 32; // register width in bits + localparam DIO_DIRECTION_REGISTER_MASK = 32'hFFF0FFF; + localparam DIO_DIRECTION_A_SIZE = 12; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_A + localparam DIO_DIRECTION_A_MSB = 11; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_A + localparam DIO_DIRECTION_A = 0; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_A + localparam DIO_DIRECTION_B_SIZE = 12; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_B + localparam DIO_DIRECTION_B_MSB = 27; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_B + localparam DIO_DIRECTION_B = 16; //DIO_DIRECTION_REGISTER:DIO_DIRECTION_B + + // DIO_INPUT_REGISTER Register (from x4xx_dio.v) + localparam DIO_INPUT_REGISTER = 'h8; // Register Offset + localparam DIO_INPUT_REGISTER_SIZE = 32; // register width in bits + localparam DIO_INPUT_REGISTER_MASK = 32'hFFF0FFF; + localparam DIO_INPUT_A_SIZE = 12; //DIO_INPUT_REGISTER:DIO_INPUT_A + localparam DIO_INPUT_A_MSB = 11; //DIO_INPUT_REGISTER:DIO_INPUT_A + localparam DIO_INPUT_A = 0; //DIO_INPUT_REGISTER:DIO_INPUT_A + localparam DIO_INPUT_B_SIZE = 12; //DIO_INPUT_REGISTER:DIO_INPUT_B + localparam DIO_INPUT_B_MSB = 27; //DIO_INPUT_REGISTER:DIO_INPUT_B + localparam DIO_INPUT_B = 16; //DIO_INPUT_REGISTER:DIO_INPUT_B + + // DIO_OUTPUT_REGISTER Register (from x4xx_dio.v) + localparam DIO_OUTPUT_REGISTER = 'hC; // Register Offset + localparam DIO_OUTPUT_REGISTER_SIZE = 32; // register width in bits + localparam DIO_OUTPUT_REGISTER_MASK = 32'hFFF0FFF; + localparam DIO_OUTPUT_A_SIZE = 12; //DIO_OUTPUT_REGISTER:DIO_OUTPUT_A + localparam DIO_OUTPUT_A_MSB = 11; //DIO_OUTPUT_REGISTER:DIO_OUTPUT_A + localparam DIO_OUTPUT_A = 0; //DIO_OUTPUT_REGISTER:DIO_OUTPUT_A + localparam DIO_OUTPUT_B_SIZE = 12; //DIO_OUTPUT_REGISTER:DIO_OUTPUT_B + localparam DIO_OUTPUT_B_MSB = 27; //DIO_OUTPUT_REGISTER:DIO_OUTPUT_B + localparam DIO_OUTPUT_B = 16; //DIO_OUTPUT_REGISTER:DIO_OUTPUT_B diff --git a/fpga/usrp3/top/x400/regmap/global_regs_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/global_regs_regmap_utils.vh new file mode 100644 index 000000000..bc1ab7778 --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/global_regs_regmap_utils.vh @@ -0,0 +1,276 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: global_regs_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // COMPAT_NUM_REG : 0x0 (x4xx_global_regs.v) + // DATESTAMP_REG : 0x4 (x4xx_global_regs.v) + // GIT_HASH_REG : 0x8 (x4xx_global_regs.v) + // SCRATCH_REG : 0xC (x4xx_global_regs.v) + // DEVICE_ID_REG : 0x10 (x4xx_global_regs.v) + // RFNOC_INFO_REG : 0x14 (x4xx_global_regs.v) + // CLOCK_CTRL_REG : 0x18 (x4xx_global_regs.v) + // PPS_CTRL_REG : 0x1C (x4xx_global_regs.v) + // CHDR_CLK_RATE_REG : 0x20 (x4xx_global_regs.v) + // CHDR_CLK_COUNT_REG : 0x24 (x4xx_global_regs.v) + // GPS_CTRL_REG : 0x38 (x4xx_global_regs.v) + // GPS_STATUS_REG : 0x3C (x4xx_global_regs.v) + // DBOARD_CTRL_REG : 0x40 (x4xx_global_regs.v) + // DBOARD_STATUS_REG : 0x44 (x4xx_global_regs.v) + // NUM_TIMEKEEPERS_REG : 0x48 (x4xx_global_regs.v) + // SERIAL_NUM_LOW_REG : 0x4C (x4xx_global_regs.v) + // SERIAL_NUM_HIGH_REG : 0x50 (x4xx_global_regs.v) + // MFG_TEST_CTRL_REG : 0x54 (x4xx_global_regs.v) + // MFG_TEST_STATUS_REG : 0x58 (x4xx_global_regs.v) + // QSFP_PORT_0_0_INFO_REG : 0x60 (x4xx_global_regs.v) + // QSFP_PORT_0_1_INFO_REG : 0x64 (x4xx_global_regs.v) + // QSFP_PORT_0_2_INFO_REG : 0x68 (x4xx_global_regs.v) + // QSFP_PORT_0_3_INFO_REG : 0x6C (x4xx_global_regs.v) + // QSFP_PORT_1_0_INFO_REG : 0x70 (x4xx_global_regs.v) + // QSFP_PORT_1_1_INFO_REG : 0x74 (x4xx_global_regs.v) + // QSFP_PORT_1_2_INFO_REG : 0x78 (x4xx_global_regs.v) + // QSFP_PORT_1_3_INFO_REG : 0x7C (x4xx_global_regs.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group GLOBAL_REGS +//=============================================================================== + + // COMPAT_NUM_REG Register (from x4xx_global_regs.v) + localparam COMPAT_NUM_REG = 'h0; // Register Offset + localparam COMPAT_NUM_REG_SIZE = 32; // register width in bits + localparam COMPAT_NUM_REG_MASK = 32'hFFFFFFFF; + localparam COMPAT_MINOR_SIZE = 16; //COMPAT_NUM_REG:COMPAT_MINOR + localparam COMPAT_MINOR_MSB = 15; //COMPAT_NUM_REG:COMPAT_MINOR + localparam COMPAT_MINOR = 0; //COMPAT_NUM_REG:COMPAT_MINOR + localparam COMPAT_MAJOR_SIZE = 16; //COMPAT_NUM_REG:COMPAT_MAJOR + localparam COMPAT_MAJOR_MSB = 31; //COMPAT_NUM_REG:COMPAT_MAJOR + localparam COMPAT_MAJOR = 16; //COMPAT_NUM_REG:COMPAT_MAJOR + + // DATESTAMP_REG Register (from x4xx_global_regs.v) + localparam DATESTAMP_REG = 'h4; // Register Offset + localparam DATESTAMP_REG_SIZE = 32; // register width in bits + localparam DATESTAMP_REG_MASK = 32'hFFFFFFFF; + localparam SECONDS_SIZE = 6; //DATESTAMP_REG:SECONDS + localparam SECONDS_MSB = 5; //DATESTAMP_REG:SECONDS + localparam SECONDS = 0; //DATESTAMP_REG:SECONDS + localparam MINUTES_SIZE = 6; //DATESTAMP_REG:MINUTES + localparam MINUTES_MSB = 11; //DATESTAMP_REG:MINUTES + localparam MINUTES = 6; //DATESTAMP_REG:MINUTES + localparam HOUR_SIZE = 5; //DATESTAMP_REG:HOUR + localparam HOUR_MSB = 16; //DATESTAMP_REG:HOUR + localparam HOUR = 12; //DATESTAMP_REG:HOUR + localparam YEAR_SIZE = 6; //DATESTAMP_REG:YEAR + localparam YEAR_MSB = 22; //DATESTAMP_REG:YEAR + localparam YEAR = 17; //DATESTAMP_REG:YEAR + localparam MONTH_SIZE = 4; //DATESTAMP_REG:MONTH + localparam MONTH_MSB = 26; //DATESTAMP_REG:MONTH + localparam MONTH = 23; //DATESTAMP_REG:MONTH + localparam DAY_SIZE = 5; //DATESTAMP_REG:DAY + localparam DAY_MSB = 31; //DATESTAMP_REG:DAY + localparam DAY = 27; //DATESTAMP_REG:DAY + + // GIT_HASH_REG Register (from x4xx_global_regs.v) + localparam GIT_HASH_REG = 'h8; // Register Offset + localparam GIT_HASH_REG_SIZE = 32; // register width in bits + localparam GIT_HASH_REG_MASK = 32'h0; + + // SCRATCH_REG Register (from x4xx_global_regs.v) + localparam SCRATCH_REG = 'hC; // Register Offset + localparam SCRATCH_REG_SIZE = 32; // register width in bits + localparam SCRATCH_REG_MASK = 32'h0; + + // DEVICE_ID_REG Register (from x4xx_global_regs.v) + localparam DEVICE_ID_REG = 'h10; // Register Offset + localparam DEVICE_ID_REG_SIZE = 32; // register width in bits + localparam DEVICE_ID_REG_MASK = 32'h8000FFFF; + localparam DEVICE_ID_SIZE = 16; //DEVICE_ID_REG:DEVICE_ID + localparam DEVICE_ID_MSB = 15; //DEVICE_ID_REG:DEVICE_ID + localparam DEVICE_ID = 0; //DEVICE_ID_REG:DEVICE_ID + localparam PCIE_PRESENT_BIT_SIZE = 1; //DEVICE_ID_REG:PCIE_PRESENT_BIT + localparam PCIE_PRESENT_BIT_MSB = 31; //DEVICE_ID_REG:PCIE_PRESENT_BIT + localparam PCIE_PRESENT_BIT = 31; //DEVICE_ID_REG:PCIE_PRESENT_BIT + + // RFNOC_INFO_REG Register (from x4xx_global_regs.v) + localparam RFNOC_INFO_REG = 'h14; // Register Offset + localparam RFNOC_INFO_REG_SIZE = 32; // register width in bits + localparam RFNOC_INFO_REG_MASK = 32'hFFFFFFFF; + localparam RFNOC_PROTO_MINOR_SIZE = 8; //RFNOC_INFO_REG:RFNOC_PROTO_MINOR + localparam RFNOC_PROTO_MINOR_MSB = 7; //RFNOC_INFO_REG:RFNOC_PROTO_MINOR + localparam RFNOC_PROTO_MINOR = 0; //RFNOC_INFO_REG:RFNOC_PROTO_MINOR + localparam RFNOC_PROTO_MAJOR_SIZE = 8; //RFNOC_INFO_REG:RFNOC_PROTO_MAJOR + localparam RFNOC_PROTO_MAJOR_MSB = 15; //RFNOC_INFO_REG:RFNOC_PROTO_MAJOR + localparam RFNOC_PROTO_MAJOR = 8; //RFNOC_INFO_REG:RFNOC_PROTO_MAJOR + localparam CHDR_WIDTH_SIZE = 16; //RFNOC_INFO_REG:CHDR_WIDTH + localparam CHDR_WIDTH_MSB = 31; //RFNOC_INFO_REG:CHDR_WIDTH + localparam CHDR_WIDTH = 16; //RFNOC_INFO_REG:CHDR_WIDTH + + // CLOCK_CTRL_REG Register (from x4xx_global_regs.v) + localparam CLOCK_CTRL_REG = 'h18; // Register Offset + localparam CLOCK_CTRL_REG_SIZE = 32; // register width in bits + localparam CLOCK_CTRL_REG_MASK = 32'hFFFF033F; + localparam PPS_SELECT_SIZE = 2; //CLOCK_CTRL_REG:PPS_SELECT + localparam PPS_SELECT_MSB = 1; //CLOCK_CTRL_REG:PPS_SELECT + localparam PPS_SELECT = 0; //CLOCK_CTRL_REG:PPS_SELECT + localparam PPS_ENUM_SIZE = 3; + localparam PPS_INT_25MHZ = 'h0; // enum value + localparam PPS_INT_10MHZ = 'h1; // enum value + localparam PPS_EXT = 'h2; // enum value + localparam REF_SELECT_SIZE = 1; //CLOCK_CTRL_REG:REF_SELECT + localparam REF_SELECT_MSB = 2; //CLOCK_CTRL_REG:REF_SELECT + localparam REF_SELECT = 2; //CLOCK_CTRL_REG:REF_SELECT + localparam REFCLK_LOCKED_SIZE = 1; //CLOCK_CTRL_REG:REFCLK_LOCKED + localparam REFCLK_LOCKED_MSB = 3; //CLOCK_CTRL_REG:REFCLK_LOCKED + localparam REFCLK_LOCKED = 3; //CLOCK_CTRL_REG:REFCLK_LOCKED + localparam TRIGGER_IO_SELECT_SIZE = 2; //CLOCK_CTRL_REG:TRIGGER_IO_SELECT + localparam TRIGGER_IO_SELECT_MSB = 5; //CLOCK_CTRL_REG:TRIGGER_IO_SELECT + localparam TRIGGER_IO_SELECT = 4; //CLOCK_CTRL_REG:TRIGGER_IO_SELECT + localparam TRIG_IO_ENUM_SIZE = 2; + localparam TRIG_IO_INPUT = 'h0; // enum value + localparam TRIG_IO_PPS_OUTPUT = 'h1; // enum value + localparam PLL_SYNC_TRIGGER_SIZE = 1; //CLOCK_CTRL_REG:PLL_SYNC_TRIGGER + localparam PLL_SYNC_TRIGGER_MSB = 8; //CLOCK_CTRL_REG:PLL_SYNC_TRIGGER + localparam PLL_SYNC_TRIGGER = 8; //CLOCK_CTRL_REG:PLL_SYNC_TRIGGER + localparam PLL_SYNC_DONE_SIZE = 1; //CLOCK_CTRL_REG:PLL_SYNC_DONE + localparam PLL_SYNC_DONE_MSB = 9; //CLOCK_CTRL_REG:PLL_SYNC_DONE + localparam PLL_SYNC_DONE = 9; //CLOCK_CTRL_REG:PLL_SYNC_DONE + localparam PLL_SYNC_DELAY_SIZE = 8; //CLOCK_CTRL_REG:PLL_SYNC_DELAY + localparam PLL_SYNC_DELAY_MSB = 23; //CLOCK_CTRL_REG:PLL_SYNC_DELAY + localparam PLL_SYNC_DELAY = 16; //CLOCK_CTRL_REG:PLL_SYNC_DELAY + localparam PPS_BRC_DELAY_SIZE = 8; //CLOCK_CTRL_REG:PPS_BRC_DELAY + localparam PPS_BRC_DELAY_MSB = 31; //CLOCK_CTRL_REG:PPS_BRC_DELAY + localparam PPS_BRC_DELAY = 24; //CLOCK_CTRL_REG:PPS_BRC_DELAY + + // PPS_CTRL_REG Register (from x4xx_global_regs.v) + localparam PPS_CTRL_REG = 'h1C; // Register Offset + localparam PPS_CTRL_REG_SIZE = 32; // register width in bits + localparam PPS_CTRL_REG_MASK = 32'hB3FFFFFF; + localparam PPS_PRC_DELAY_SIZE = 26; //PPS_CTRL_REG:PPS_PRC_DELAY + localparam PPS_PRC_DELAY_MSB = 25; //PPS_CTRL_REG:PPS_PRC_DELAY + localparam PPS_PRC_DELAY = 0; //PPS_CTRL_REG:PPS_PRC_DELAY + localparam PRC_RC_DIVIDER_SIZE = 2; //PPS_CTRL_REG:PRC_RC_DIVIDER + localparam PRC_RC_DIVIDER_MSB = 29; //PPS_CTRL_REG:PRC_RC_DIVIDER + localparam PRC_RC_DIVIDER = 28; //PPS_CTRL_REG:PRC_RC_DIVIDER + localparam PPS_RC_ENABLED_SIZE = 1; //PPS_CTRL_REG:PPS_RC_ENABLED + localparam PPS_RC_ENABLED_MSB = 31; //PPS_CTRL_REG:PPS_RC_ENABLED + localparam PPS_RC_ENABLED = 31; //PPS_CTRL_REG:PPS_RC_ENABLED + + // CHDR_CLK_RATE_REG Register (from x4xx_global_regs.v) + localparam CHDR_CLK_RATE_REG = 'h20; // Register Offset + localparam CHDR_CLK_RATE_REG_SIZE = 32; // register width in bits + localparam CHDR_CLK_RATE_REG_MASK = 32'hFFFFFFFF; + localparam CHDR_CLK_SIZE = 32; //CHDR_CLK_RATE_REG:CHDR_CLK + localparam CHDR_CLK_MSB = 31; //CHDR_CLK_RATE_REG:CHDR_CLK + localparam CHDR_CLK = 0; //CHDR_CLK_RATE_REG:CHDR_CLK + localparam CHDR_CLK_ENUM_SIZE = 1; + localparam CHDR_CLK_VALUE = 'hBEBC200; // enum value + + // CHDR_CLK_COUNT_REG Register (from x4xx_global_regs.v) + localparam CHDR_CLK_COUNT_REG = 'h24; // Register Offset + localparam CHDR_CLK_COUNT_REG_SIZE = 32; // register width in bits + localparam CHDR_CLK_COUNT_REG_MASK = 32'h0; + + // GPS_CTRL_REG Register (from x4xx_global_regs.v) + localparam GPS_CTRL_REG = 'h38; // Register Offset + localparam GPS_CTRL_REG_SIZE = 32; // register width in bits + localparam GPS_CTRL_REG_MASK = 32'h0; + + // GPS_STATUS_REG Register (from x4xx_global_regs.v) + localparam GPS_STATUS_REG = 'h3C; // Register Offset + localparam GPS_STATUS_REG_SIZE = 32; // register width in bits + localparam GPS_STATUS_REG_MASK = 32'h0; + + // DBOARD_CTRL_REG Register (from x4xx_global_regs.v) + localparam DBOARD_CTRL_REG = 'h40; // Register Offset + localparam DBOARD_CTRL_REG_SIZE = 32; // register width in bits + localparam DBOARD_CTRL_REG_MASK = 32'h0; + + // DBOARD_STATUS_REG Register (from x4xx_global_regs.v) + localparam DBOARD_STATUS_REG = 'h44; // Register Offset + localparam DBOARD_STATUS_REG_SIZE = 32; // register width in bits + localparam DBOARD_STATUS_REG_MASK = 32'h0; + + // NUM_TIMEKEEPERS_REG Register (from x4xx_global_regs.v) + localparam NUM_TIMEKEEPERS_REG = 'h48; // Register Offset + localparam NUM_TIMEKEEPERS_REG_SIZE = 32; // register width in bits + localparam NUM_TIMEKEEPERS_REG_MASK = 32'h0; + + // SERIAL_NUM_LOW_REG Register (from x4xx_global_regs.v) + localparam SERIAL_NUM_LOW_REG = 'h4C; // Register Offset + localparam SERIAL_NUM_LOW_REG_SIZE = 32; // register width in bits + localparam SERIAL_NUM_LOW_REG_MASK = 32'h0; + + // SERIAL_NUM_HIGH_REG Register (from x4xx_global_regs.v) + localparam SERIAL_NUM_HIGH_REG = 'h50; // Register Offset + localparam SERIAL_NUM_HIGH_REG_SIZE = 32; // register width in bits + localparam SERIAL_NUM_HIGH_REG_MASK = 32'h0; + + // MFG_TEST_CTRL_REG Register (from x4xx_global_regs.v) + localparam MFG_TEST_CTRL_REG = 'h54; // Register Offset + localparam MFG_TEST_CTRL_REG_SIZE = 32; // register width in bits + localparam MFG_TEST_CTRL_REG_MASK = 32'h3; + localparam MFG_TEST_EN_GTY_RCV_CLK_SIZE = 1; //MFG_TEST_CTRL_REG:MFG_TEST_EN_GTY_RCV_CLK + localparam MFG_TEST_EN_GTY_RCV_CLK_MSB = 0; //MFG_TEST_CTRL_REG:MFG_TEST_EN_GTY_RCV_CLK + localparam MFG_TEST_EN_GTY_RCV_CLK = 0; //MFG_TEST_CTRL_REG:MFG_TEST_EN_GTY_RCV_CLK + localparam MFG_TEST_EN_FABRIC_CLK_SIZE = 1; //MFG_TEST_CTRL_REG:MFG_TEST_EN_FABRIC_CLK + localparam MFG_TEST_EN_FABRIC_CLK_MSB = 1; //MFG_TEST_CTRL_REG:MFG_TEST_EN_FABRIC_CLK + localparam MFG_TEST_EN_FABRIC_CLK = 1; //MFG_TEST_CTRL_REG:MFG_TEST_EN_FABRIC_CLK + + // MFG_TEST_STATUS_REG Register (from x4xx_global_regs.v) + localparam MFG_TEST_STATUS_REG = 'h58; // Register Offset + localparam MFG_TEST_STATUS_REG_SIZE = 32; // register width in bits + localparam MFG_TEST_STATUS_REG_MASK = 32'h3FFFFFF; + localparam MFG_TEST_FPGA_AUX_REF_FREQ_SIZE = 26; //MFG_TEST_STATUS_REG:MFG_TEST_FPGA_AUX_REF_FREQ + localparam MFG_TEST_FPGA_AUX_REF_FREQ_MSB = 25; //MFG_TEST_STATUS_REG:MFG_TEST_FPGA_AUX_REF_FREQ + localparam MFG_TEST_FPGA_AUX_REF_FREQ = 0; //MFG_TEST_STATUS_REG:MFG_TEST_FPGA_AUX_REF_FREQ + + // QSFP_PORT_0_0_INFO_REG Register (from x4xx_global_regs.v) + localparam QSFP_PORT_0_0_INFO_REG = 'h60; // Register Offset + localparam QSFP_PORT_0_0_INFO_REG_SIZE = 32; // register width in bits + localparam QSFP_PORT_0_0_INFO_REG_MASK = 32'h0; + + // QSFP_PORT_0_1_INFO_REG Register (from x4xx_global_regs.v) + localparam QSFP_PORT_0_1_INFO_REG = 'h64; // Register Offset + localparam QSFP_PORT_0_1_INFO_REG_SIZE = 32; // register width in bits + localparam QSFP_PORT_0_1_INFO_REG_MASK = 32'h0; + + // QSFP_PORT_0_2_INFO_REG Register (from x4xx_global_regs.v) + localparam QSFP_PORT_0_2_INFO_REG = 'h68; // Register Offset + localparam QSFP_PORT_0_2_INFO_REG_SIZE = 32; // register width in bits + localparam QSFP_PORT_0_2_INFO_REG_MASK = 32'h0; + + // QSFP_PORT_0_3_INFO_REG Register (from x4xx_global_regs.v) + localparam QSFP_PORT_0_3_INFO_REG = 'h6C; // Register Offset + localparam QSFP_PORT_0_3_INFO_REG_SIZE = 32; // register width in bits + localparam QSFP_PORT_0_3_INFO_REG_MASK = 32'h0; + + // QSFP_PORT_1_0_INFO_REG Register (from x4xx_global_regs.v) + localparam QSFP_PORT_1_0_INFO_REG = 'h70; // Register Offset + localparam QSFP_PORT_1_0_INFO_REG_SIZE = 32; // register width in bits + localparam QSFP_PORT_1_0_INFO_REG_MASK = 32'h0; + + // QSFP_PORT_1_1_INFO_REG Register (from x4xx_global_regs.v) + localparam QSFP_PORT_1_1_INFO_REG = 'h74; // Register Offset + localparam QSFP_PORT_1_1_INFO_REG_SIZE = 32; // register width in bits + localparam QSFP_PORT_1_1_INFO_REG_MASK = 32'h0; + + // QSFP_PORT_1_2_INFO_REG Register (from x4xx_global_regs.v) + localparam QSFP_PORT_1_2_INFO_REG = 'h78; // Register Offset + localparam QSFP_PORT_1_2_INFO_REG_SIZE = 32; // register width in bits + localparam QSFP_PORT_1_2_INFO_REG_MASK = 32'h0; + + // QSFP_PORT_1_3_INFO_REG Register (from x4xx_global_regs.v) + localparam QSFP_PORT_1_3_INFO_REG = 'h7C; // Register Offset + localparam QSFP_PORT_1_3_INFO_REG_SIZE = 32; // register width in bits + localparam QSFP_PORT_1_3_INFO_REG_MASK = 32'h0; diff --git a/fpga/usrp3/top/x400/regmap/pl_cpld_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/pl_cpld_regmap_utils.vh new file mode 100644 index 000000000..05e5a48af --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/pl_cpld_regmap_utils.vh @@ -0,0 +1,41 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: pl_cpld_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // BASE : 0x0 (cpld_interface.v) + // MB_CPLD : 0x8000 (cpld_interface.v) + // DB0_CPLD : 0x10000 (cpld_interface.v) + // DB1_CPLD : 0x18000 (cpld_interface.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group PL_CPLD_WINDOWS +//=============================================================================== + + // BASE Window (from cpld_interface.v) + localparam BASE = 'h0; // Window Offset + localparam BASE_SIZE = 'h40; // size in bytes + + // MB_CPLD Window (from cpld_interface.v) + localparam MB_CPLD = 'h8000; // Window Offset + localparam MB_CPLD_SIZE = 'h8000; // size in bytes + + // DB0_CPLD Window (from cpld_interface.v) + localparam DB0_CPLD = 'h10000; // Window Offset + localparam DB0_CPLD_SIZE = 'h8000; // size in bytes + + // DB1_CPLD Window (from cpld_interface.v) + localparam DB1_CPLD = 'h18000; // Window Offset + localparam DB1_CPLD_SIZE = 'h8000; // size in bytes diff --git a/fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh new file mode 100644 index 000000000..18d442cd1 --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/radio_ctrlport_regmap_utils.vh @@ -0,0 +1,31 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: radio_ctrlport_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // DB_WINDOW : 0x0 (rfdc_timing_control.v) + // RFDC_TIMING_WINDOW : 0x8000 (rfdc_timing_control.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group RADIO_CTRLPORT_WINDOWS +//=============================================================================== + + // DB_WINDOW Window (from rfdc_timing_control.v) + localparam DB_WINDOW = 'h0; // Window Offset + localparam DB_WINDOW_SIZE = 'h8000; // size in bytes + + // RFDC_TIMING_WINDOW Window (from rfdc_timing_control.v) + localparam RFDC_TIMING_WINDOW = 'h8000; // Window Offset + localparam RFDC_TIMING_WINDOW_SIZE = 'h8000; // size in bytes diff --git a/fpga/usrp3/top/x400/regmap/rfdc_regs_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/rfdc_regs_regmap_utils.vh new file mode 100644 index 000000000..8a6c5aa9b --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/rfdc_regs_regmap_utils.vh @@ -0,0 +1,303 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rfdc_regs_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // MMCM : 0x0 (common_regs.v) + // INVERT_IQ_REG : 0x10000 (common_regs.v) + // MMCM_RESET_REG : 0x11000 (common_regs.v) + // RF_RESET_CONTROL_REG : 0x12000 (common_regs.v) + // RF_RESET_STATUS_REG : 0x12008 (common_regs.v) + // RF_AXI_STATUS_REG : 0x13000 (common_regs.v) + // FABRIC_DSP_REG : 0x13008 (common_regs.v) + // CALIBRATION_DATA : 0x14000 (common_regs.v) + // CALIBRATION_ENABLE : 0x14008 (common_regs.v) + // THRESHOLD_STATUS : 0x15000 (common_regs.v) + // RF_PLL_CONTROL_REG : 0x16000 (common_regs.v) + // RF_PLL_STATUS_REG : 0x16008 (common_regs.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group RFDC_REGS +//=============================================================================== + + // Enumerated type FABRIC_DSP_BW_ENUM + localparam FABRIC_DSP_BW_ENUM_SIZE = 4; + localparam FABRIC_DSP_BW_NONE = 'h0; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_NONE + localparam FABRIC_DSP_BW_100M = 'h64; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_100M + localparam FABRIC_DSP_BW_200M = 'hC8; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_200M + localparam FABRIC_DSP_BW_400M = 'h190; // FABRIC_DSP_BW_ENUM:FABRIC_DSP_BW_400M + + // MMCM Window (from common_regs.v) + localparam MMCM = 'h0; // Window Offset + localparam MMCM_SIZE = 'h10000; // size in bytes + + // INVERT_IQ_REG Register (from common_regs.v) + localparam INVERT_IQ_REG = 'h10000; // Register Offset + localparam INVERT_IQ_REG_SIZE = 32; // register width in bits + localparam INVERT_IQ_REG_MASK = 32'hFFFF; + localparam INVERT_DB0_ADC0_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_ADC0_IQ + localparam INVERT_DB0_ADC0_IQ_MSB = 0; //INVERT_IQ_REG:INVERT_DB0_ADC0_IQ + localparam INVERT_DB0_ADC0_IQ = 0; //INVERT_IQ_REG:INVERT_DB0_ADC0_IQ + localparam INVERT_DB0_ADC1_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_ADC1_IQ + localparam INVERT_DB0_ADC1_IQ_MSB = 1; //INVERT_IQ_REG:INVERT_DB0_ADC1_IQ + localparam INVERT_DB0_ADC1_IQ = 1; //INVERT_IQ_REG:INVERT_DB0_ADC1_IQ + localparam INVERT_DB0_ADC2_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_ADC2_IQ + localparam INVERT_DB0_ADC2_IQ_MSB = 2; //INVERT_IQ_REG:INVERT_DB0_ADC2_IQ + localparam INVERT_DB0_ADC2_IQ = 2; //INVERT_IQ_REG:INVERT_DB0_ADC2_IQ + localparam INVERT_DB0_ADC3_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_ADC3_IQ + localparam INVERT_DB0_ADC3_IQ_MSB = 3; //INVERT_IQ_REG:INVERT_DB0_ADC3_IQ + localparam INVERT_DB0_ADC3_IQ = 3; //INVERT_IQ_REG:INVERT_DB0_ADC3_IQ + localparam INVERT_DB1_ADC0_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_ADC0_IQ + localparam INVERT_DB1_ADC0_IQ_MSB = 4; //INVERT_IQ_REG:INVERT_DB1_ADC0_IQ + localparam INVERT_DB1_ADC0_IQ = 4; //INVERT_IQ_REG:INVERT_DB1_ADC0_IQ + localparam INVERT_DB1_ADC1_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_ADC1_IQ + localparam INVERT_DB1_ADC1_IQ_MSB = 5; //INVERT_IQ_REG:INVERT_DB1_ADC1_IQ + localparam INVERT_DB1_ADC1_IQ = 5; //INVERT_IQ_REG:INVERT_DB1_ADC1_IQ + localparam INVERT_DB1_ADC2_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_ADC2_IQ + localparam INVERT_DB1_ADC2_IQ_MSB = 6; //INVERT_IQ_REG:INVERT_DB1_ADC2_IQ + localparam INVERT_DB1_ADC2_IQ = 6; //INVERT_IQ_REG:INVERT_DB1_ADC2_IQ + localparam INVERT_DB1_ADC3_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_ADC3_IQ + localparam INVERT_DB1_ADC3_IQ_MSB = 7; //INVERT_IQ_REG:INVERT_DB1_ADC3_IQ + localparam INVERT_DB1_ADC3_IQ = 7; //INVERT_IQ_REG:INVERT_DB1_ADC3_IQ + localparam INVERT_DB0_DAC0_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_DAC0_IQ + localparam INVERT_DB0_DAC0_IQ_MSB = 8; //INVERT_IQ_REG:INVERT_DB0_DAC0_IQ + localparam INVERT_DB0_DAC0_IQ = 8; //INVERT_IQ_REG:INVERT_DB0_DAC0_IQ + localparam INVERT_DB0_DAC1_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_DAC1_IQ + localparam INVERT_DB0_DAC1_IQ_MSB = 9; //INVERT_IQ_REG:INVERT_DB0_DAC1_IQ + localparam INVERT_DB0_DAC1_IQ = 9; //INVERT_IQ_REG:INVERT_DB0_DAC1_IQ + localparam INVERT_DB0_DAC2_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_DAC2_IQ + localparam INVERT_DB0_DAC2_IQ_MSB = 10; //INVERT_IQ_REG:INVERT_DB0_DAC2_IQ + localparam INVERT_DB0_DAC2_IQ = 10; //INVERT_IQ_REG:INVERT_DB0_DAC2_IQ + localparam INVERT_DB0_DAC3_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB0_DAC3_IQ + localparam INVERT_DB0_DAC3_IQ_MSB = 11; //INVERT_IQ_REG:INVERT_DB0_DAC3_IQ + localparam INVERT_DB0_DAC3_IQ = 11; //INVERT_IQ_REG:INVERT_DB0_DAC3_IQ + localparam INVERT_DB1_DAC0_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_DAC0_IQ + localparam INVERT_DB1_DAC0_IQ_MSB = 12; //INVERT_IQ_REG:INVERT_DB1_DAC0_IQ + localparam INVERT_DB1_DAC0_IQ = 12; //INVERT_IQ_REG:INVERT_DB1_DAC0_IQ + localparam INVERT_DB1_DAC1_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_DAC1_IQ + localparam INVERT_DB1_DAC1_IQ_MSB = 13; //INVERT_IQ_REG:INVERT_DB1_DAC1_IQ + localparam INVERT_DB1_DAC1_IQ = 13; //INVERT_IQ_REG:INVERT_DB1_DAC1_IQ + localparam INVERT_DB1_DAC2_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_DAC2_IQ + localparam INVERT_DB1_DAC2_IQ_MSB = 14; //INVERT_IQ_REG:INVERT_DB1_DAC2_IQ + localparam INVERT_DB1_DAC2_IQ = 14; //INVERT_IQ_REG:INVERT_DB1_DAC2_IQ + localparam INVERT_DB1_DAC3_IQ_SIZE = 1; //INVERT_IQ_REG:INVERT_DB1_DAC3_IQ + localparam INVERT_DB1_DAC3_IQ_MSB = 15; //INVERT_IQ_REG:INVERT_DB1_DAC3_IQ + localparam INVERT_DB1_DAC3_IQ = 15; //INVERT_IQ_REG:INVERT_DB1_DAC3_IQ + + // MMCM_RESET_REG Register (from common_regs.v) + localparam MMCM_RESET_REG = 'h11000; // Register Offset + localparam MMCM_RESET_REG_SIZE = 32; // register width in bits + localparam MMCM_RESET_REG_MASK = 32'h1; + localparam RESET_MMCM_SIZE = 1; //MMCM_RESET_REG:RESET_MMCM + localparam RESET_MMCM_MSB = 0; //MMCM_RESET_REG:RESET_MMCM + localparam RESET_MMCM = 0; //MMCM_RESET_REG:RESET_MMCM + + // RF_RESET_CONTROL_REG Register (from common_regs.v) + localparam RF_RESET_CONTROL_REG = 'h12000; // Register Offset + localparam RF_RESET_CONTROL_REG_SIZE = 32; // register width in bits + localparam RF_RESET_CONTROL_REG_MASK = 32'h331; + localparam FSM_RESET_SIZE = 1; //RF_RESET_CONTROL_REG:FSM_RESET + localparam FSM_RESET_MSB = 0; //RF_RESET_CONTROL_REG:FSM_RESET + localparam FSM_RESET = 0; //RF_RESET_CONTROL_REG:FSM_RESET + localparam ADC_RESET_SIZE = 1; //RF_RESET_CONTROL_REG:ADC_RESET + localparam ADC_RESET_MSB = 4; //RF_RESET_CONTROL_REG:ADC_RESET + localparam ADC_RESET = 4; //RF_RESET_CONTROL_REG:ADC_RESET + localparam ADC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REG:ADC_ENABLE + localparam ADC_ENABLE_MSB = 5; //RF_RESET_CONTROL_REG:ADC_ENABLE + localparam ADC_ENABLE = 5; //RF_RESET_CONTROL_REG:ADC_ENABLE + localparam DAC_RESET_SIZE = 1; //RF_RESET_CONTROL_REG:DAC_RESET + localparam DAC_RESET_MSB = 8; //RF_RESET_CONTROL_REG:DAC_RESET + localparam DAC_RESET = 8; //RF_RESET_CONTROL_REG:DAC_RESET + localparam DAC_ENABLE_SIZE = 1; //RF_RESET_CONTROL_REG:DAC_ENABLE + localparam DAC_ENABLE_MSB = 9; //RF_RESET_CONTROL_REG:DAC_ENABLE + localparam DAC_ENABLE = 9; //RF_RESET_CONTROL_REG:DAC_ENABLE + + // RF_RESET_STATUS_REG Register (from common_regs.v) + localparam RF_RESET_STATUS_REG = 'h12008; // Register Offset + localparam RF_RESET_STATUS_REG_SIZE = 32; // register width in bits + localparam RF_RESET_STATUS_REG_MASK = 32'h888; + localparam FSM_RESET_DONE_SIZE = 1; //RF_RESET_STATUS_REG:FSM_RESET_DONE + localparam FSM_RESET_DONE_MSB = 3; //RF_RESET_STATUS_REG:FSM_RESET_DONE + localparam FSM_RESET_DONE = 3; //RF_RESET_STATUS_REG:FSM_RESET_DONE + localparam ADC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REG:ADC_SEQ_DONE + localparam ADC_SEQ_DONE_MSB = 7; //RF_RESET_STATUS_REG:ADC_SEQ_DONE + localparam ADC_SEQ_DONE = 7; //RF_RESET_STATUS_REG:ADC_SEQ_DONE + localparam DAC_SEQ_DONE_SIZE = 1; //RF_RESET_STATUS_REG:DAC_SEQ_DONE + localparam DAC_SEQ_DONE_MSB = 11; //RF_RESET_STATUS_REG:DAC_SEQ_DONE + localparam DAC_SEQ_DONE = 11; //RF_RESET_STATUS_REG:DAC_SEQ_DONE + + // RF_AXI_STATUS_REG Register (from common_regs.v) + localparam RF_AXI_STATUS_REG = 'h13000; // Register Offset + localparam RF_AXI_STATUS_REG_SIZE = 32; // register width in bits + localparam RF_AXI_STATUS_REG_MASK = 32'hFFFFFFFF; + localparam RFDC_DAC_TREADY_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY + localparam RFDC_DAC_TREADY_MSB = 1; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY + localparam RFDC_DAC_TREADY = 0; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY + localparam RFDC_DAC_TVALID_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID + localparam RFDC_DAC_TVALID_MSB = 3; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID + localparam RFDC_DAC_TVALID = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID + localparam RFDC_ADC_Q_TREADY_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY + localparam RFDC_ADC_Q_TREADY_MSB = 5; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY + localparam RFDC_ADC_Q_TREADY = 4; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY + localparam RFDC_ADC_I_TREADY_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY + localparam RFDC_ADC_I_TREADY_MSB = 7; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY + localparam RFDC_ADC_I_TREADY = 6; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY + localparam RFDC_ADC_Q_TVALID_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID + localparam RFDC_ADC_Q_TVALID_MSB = 9; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID + localparam RFDC_ADC_Q_TVALID = 8; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID + localparam RFDC_ADC_I_TVALID_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID + localparam RFDC_ADC_I_TVALID_MSB = 11; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID + localparam RFDC_ADC_I_TVALID = 10; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID + localparam USER_ADC_TVALID_SIZE = 2; //RF_AXI_STATUS_REG:USER_ADC_TVALID + localparam USER_ADC_TVALID_MSB = 13; //RF_AXI_STATUS_REG:USER_ADC_TVALID + localparam USER_ADC_TVALID = 12; //RF_AXI_STATUS_REG:USER_ADC_TVALID + localparam USER_ADC_TREADY_SIZE = 2; //RF_AXI_STATUS_REG:USER_ADC_TREADY + localparam USER_ADC_TREADY_MSB = 15; //RF_AXI_STATUS_REG:USER_ADC_TREADY + localparam USER_ADC_TREADY = 14; //RF_AXI_STATUS_REG:USER_ADC_TREADY + localparam RFDC_DAC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1 + localparam RFDC_DAC_TREADY_DB1_MSB = 17; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1 + localparam RFDC_DAC_TREADY_DB1 = 16; //RF_AXI_STATUS_REG:RFDC_DAC_TREADY_DB1 + localparam RFDC_DAC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1 + localparam RFDC_DAC_TVALID_DB1_MSB = 19; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1 + localparam RFDC_DAC_TVALID_DB1 = 18; //RF_AXI_STATUS_REG:RFDC_DAC_TVALID_DB1 + localparam RFDC_ADC_Q_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1 + localparam RFDC_ADC_Q_TREADY_DB1_MSB = 21; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1 + localparam RFDC_ADC_Q_TREADY_DB1 = 20; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TREADY_DB1 + localparam RFDC_ADC_I_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1 + localparam RFDC_ADC_I_TREADY_DB1_MSB = 23; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1 + localparam RFDC_ADC_I_TREADY_DB1 = 22; //RF_AXI_STATUS_REG:RFDC_ADC_I_TREADY_DB1 + localparam RFDC_ADC_Q_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1 + localparam RFDC_ADC_Q_TVALID_DB1_MSB = 25; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1 + localparam RFDC_ADC_Q_TVALID_DB1 = 24; //RF_AXI_STATUS_REG:RFDC_ADC_Q_TVALID_DB1 + localparam RFDC_ADC_I_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1 + localparam RFDC_ADC_I_TVALID_DB1_MSB = 27; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1 + localparam RFDC_ADC_I_TVALID_DB1 = 26; //RF_AXI_STATUS_REG:RFDC_ADC_I_TVALID_DB1 + localparam USER_ADC_TVALID_DB1_SIZE = 2; //RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1 + localparam USER_ADC_TVALID_DB1_MSB = 29; //RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1 + localparam USER_ADC_TVALID_DB1 = 28; //RF_AXI_STATUS_REG:USER_ADC_TVALID_DB1 + localparam USER_ADC_TREADY_DB1_SIZE = 2; //RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1 + localparam USER_ADC_TREADY_DB1_MSB = 31; //RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1 + localparam USER_ADC_TREADY_DB1 = 30; //RF_AXI_STATUS_REG:USER_ADC_TREADY_DB1 + + // FABRIC_DSP_REG Register (from common_regs.v) + localparam FABRIC_DSP_REG = 'h13008; // Register Offset + localparam FABRIC_DSP_REG_SIZE = 32; // register width in bits + localparam FABRIC_DSP_REG_MASK = 32'hFFFFFFFF; + localparam FABRIC_DSP_BW_SIZE = 12; //FABRIC_DSP_REG:FABRIC_DSP_BW + localparam FABRIC_DSP_BW_MSB = 11; //FABRIC_DSP_REG:FABRIC_DSP_BW + localparam FABRIC_DSP_BW = 0; //FABRIC_DSP_REG:FABRIC_DSP_BW + localparam FABRIC_DSP_RX_CNT_SIZE = 2; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT + localparam FABRIC_DSP_RX_CNT_MSB = 13; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT + localparam FABRIC_DSP_RX_CNT = 12; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT + localparam FABRIC_DSP_TX_CNT_SIZE = 2; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT + localparam FABRIC_DSP_TX_CNT_MSB = 15; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT + localparam FABRIC_DSP_TX_CNT = 14; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT + localparam FABRIC_DSP_BW_DB1_SIZE = 12; //FABRIC_DSP_REG:FABRIC_DSP_BW_DB1 + localparam FABRIC_DSP_BW_DB1_MSB = 27; //FABRIC_DSP_REG:FABRIC_DSP_BW_DB1 + localparam FABRIC_DSP_BW_DB1 = 16; //FABRIC_DSP_REG:FABRIC_DSP_BW_DB1 + localparam FABRIC_DSP_RX_CNT_DB1_SIZE = 2; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1 + localparam FABRIC_DSP_RX_CNT_DB1_MSB = 29; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1 + localparam FABRIC_DSP_RX_CNT_DB1 = 28; //FABRIC_DSP_REG:FABRIC_DSP_RX_CNT_DB1 + localparam FABRIC_DSP_TX_CNT_DB1_SIZE = 2; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1 + localparam FABRIC_DSP_TX_CNT_DB1_MSB = 31; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1 + localparam FABRIC_DSP_TX_CNT_DB1 = 30; //FABRIC_DSP_REG:FABRIC_DSP_TX_CNT_DB1 + + // CALIBRATION_DATA Register (from common_regs.v) + localparam CALIBRATION_DATA = 'h14000; // Register Offset + localparam CALIBRATION_DATA_SIZE = 32; // register width in bits + localparam CALIBRATION_DATA_MASK = 32'hFFFFFFFF; + localparam I_DATA_SIZE = 16; //CALIBRATION_DATA:I_DATA + localparam I_DATA_MSB = 15; //CALIBRATION_DATA:I_DATA + localparam I_DATA = 0; //CALIBRATION_DATA:I_DATA + localparam Q_DATA_SIZE = 16; //CALIBRATION_DATA:Q_DATA + localparam Q_DATA_MSB = 31; //CALIBRATION_DATA:Q_DATA + localparam Q_DATA = 16; //CALIBRATION_DATA:Q_DATA + + // CALIBRATION_ENABLE Register (from common_regs.v) + localparam CALIBRATION_ENABLE = 'h14008; // Register Offset + localparam CALIBRATION_ENABLE_SIZE = 32; // register width in bits + localparam CALIBRATION_ENABLE_MASK = 32'h33; + localparam ENABLE_CALIBRATION_DATA_0_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 + localparam ENABLE_CALIBRATION_DATA_0_MSB = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 + localparam ENABLE_CALIBRATION_DATA_0 = 0; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_0 + localparam ENABLE_CALIBRATION_DATA_1_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 + localparam ENABLE_CALIBRATION_DATA_1_MSB = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 + localparam ENABLE_CALIBRATION_DATA_1 = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_1 + localparam ENABLE_CALIBRATION_DATA_2_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 + localparam ENABLE_CALIBRATION_DATA_2_MSB = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 + localparam ENABLE_CALIBRATION_DATA_2 = 4; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_2 + localparam ENABLE_CALIBRATION_DATA_3_SIZE = 1; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 + localparam ENABLE_CALIBRATION_DATA_3_MSB = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 + localparam ENABLE_CALIBRATION_DATA_3 = 5; //CALIBRATION_ENABLE:ENABLE_CALIBRATION_DATA_3 + + // THRESHOLD_STATUS Register (from common_regs.v) + localparam THRESHOLD_STATUS = 'h15000; // Register Offset + localparam THRESHOLD_STATUS_SIZE = 32; // register width in bits + localparam THRESHOLD_STATUS_MASK = 32'hF0F; + localparam ADC0_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1 + localparam ADC0_01_THRESHOLD1_MSB = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1 + localparam ADC0_01_THRESHOLD1 = 0; //THRESHOLD_STATUS:ADC0_01_THRESHOLD1 + localparam ADC0_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2 + localparam ADC0_01_THRESHOLD2_MSB = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2 + localparam ADC0_01_THRESHOLD2 = 1; //THRESHOLD_STATUS:ADC0_01_THRESHOLD2 + localparam ADC0_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1 + localparam ADC0_23_THRESHOLD1_MSB = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1 + localparam ADC0_23_THRESHOLD1 = 2; //THRESHOLD_STATUS:ADC0_23_THRESHOLD1 + localparam ADC0_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2 + localparam ADC0_23_THRESHOLD2_MSB = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2 + localparam ADC0_23_THRESHOLD2 = 3; //THRESHOLD_STATUS:ADC0_23_THRESHOLD2 + localparam ADC2_01_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1 + localparam ADC2_01_THRESHOLD1_MSB = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1 + localparam ADC2_01_THRESHOLD1 = 8; //THRESHOLD_STATUS:ADC2_01_THRESHOLD1 + localparam ADC2_01_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2 + localparam ADC2_01_THRESHOLD2_MSB = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2 + localparam ADC2_01_THRESHOLD2 = 9; //THRESHOLD_STATUS:ADC2_01_THRESHOLD2 + localparam ADC2_23_THRESHOLD1_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1 + localparam ADC2_23_THRESHOLD1_MSB = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1 + localparam ADC2_23_THRESHOLD1 = 10; //THRESHOLD_STATUS:ADC2_23_THRESHOLD1 + localparam ADC2_23_THRESHOLD2_SIZE = 1; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2 + localparam ADC2_23_THRESHOLD2_MSB = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2 + localparam ADC2_23_THRESHOLD2 = 11; //THRESHOLD_STATUS:ADC2_23_THRESHOLD2 + + // RF_PLL_CONTROL_REG Register (from common_regs.v) + localparam RF_PLL_CONTROL_REG = 'h16000; // Register Offset + localparam RF_PLL_CONTROL_REG_SIZE = 32; // register width in bits + localparam RF_PLL_CONTROL_REG_MASK = 32'h11111; + localparam ENABLE_DATA_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK + localparam ENABLE_DATA_CLK_MSB = 0; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK + localparam ENABLE_DATA_CLK = 0; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK + localparam ENABLE_DATA_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X + localparam ENABLE_DATA_CLK_2X_MSB = 4; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X + localparam ENABLE_DATA_CLK_2X = 4; //RF_PLL_CONTROL_REG:ENABLE_DATA_CLK_2X + localparam ENABLE_RF_CLK_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK + localparam ENABLE_RF_CLK_MSB = 8; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK + localparam ENABLE_RF_CLK = 8; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK + localparam ENABLE_RF_CLK_2X_SIZE = 1; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X + localparam ENABLE_RF_CLK_2X_MSB = 12; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X + localparam ENABLE_RF_CLK_2X = 12; //RF_PLL_CONTROL_REG:ENABLE_RF_CLK_2X + localparam CLEAR_DATA_CLK_UNLOCKED_SIZE = 1; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED + localparam CLEAR_DATA_CLK_UNLOCKED_MSB = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED + localparam CLEAR_DATA_CLK_UNLOCKED = 16; //RF_PLL_CONTROL_REG:CLEAR_DATA_CLK_UNLOCKED + + // RF_PLL_STATUS_REG Register (from common_regs.v) + localparam RF_PLL_STATUS_REG = 'h16008; // Register Offset + localparam RF_PLL_STATUS_REG_SIZE = 32; // register width in bits + localparam RF_PLL_STATUS_REG_MASK = 32'h110000; + localparam DATA_CLK_PLL_UNLOCKED_STICKY_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY + localparam DATA_CLK_PLL_UNLOCKED_STICKY_MSB = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY + localparam DATA_CLK_PLL_UNLOCKED_STICKY = 16; //RF_PLL_STATUS_REG:DATA_CLK_PLL_UNLOCKED_STICKY + localparam DATA_CLK_PLL_LOCKED_SIZE = 1; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED + localparam DATA_CLK_PLL_LOCKED_MSB = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED + localparam DATA_CLK_PLL_LOCKED = 20; //RF_PLL_STATUS_REG:DATA_CLK_PLL_LOCKED diff --git a/fpga/usrp3/top/x400/regmap/rfdc_timing_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/rfdc_timing_regmap_utils.vh new file mode 100644 index 000000000..545d31ff7 --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/rfdc_timing_regmap_utils.vh @@ -0,0 +1,45 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: rfdc_timing_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // NCO_RESET_REG : 0x0 (rfdc_timing_control.v) + // GEARBOX_RESET_REG : 0x4 (rfdc_timing_control.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + +//=============================================================================== +// Register Group RFDC_TIMING_REGS +//=============================================================================== + + // NCO_RESET_REG Register (from rfdc_timing_control.v) + localparam NCO_RESET_REG = 'h0; // Register Offset + localparam NCO_RESET_REG_SIZE = 32; // register width in bits + localparam NCO_RESET_REG_MASK = 32'h3; + localparam NCO_RESET_START_SIZE = 1; //NCO_RESET_REG:NCO_RESET_START + localparam NCO_RESET_START_MSB = 0; //NCO_RESET_REG:NCO_RESET_START + localparam NCO_RESET_START = 0; //NCO_RESET_REG:NCO_RESET_START + localparam NCO_RESET_DONE_SIZE = 1; //NCO_RESET_REG:NCO_RESET_DONE + localparam NCO_RESET_DONE_MSB = 1; //NCO_RESET_REG:NCO_RESET_DONE + localparam NCO_RESET_DONE = 1; //NCO_RESET_REG:NCO_RESET_DONE + + // GEARBOX_RESET_REG Register (from rfdc_timing_control.v) + localparam GEARBOX_RESET_REG = 'h4; // Register Offset + localparam GEARBOX_RESET_REG_SIZE = 32; // register width in bits + localparam GEARBOX_RESET_REG_MASK = 32'h3; + localparam ADC_RESET_SIZE = 1; //GEARBOX_RESET_REG:ADC_RESET + localparam ADC_RESET_MSB = 0; //GEARBOX_RESET_REG:ADC_RESET + localparam ADC_RESET = 0; //GEARBOX_RESET_REG:ADC_RESET + localparam DAC_RESET_SIZE = 1; //GEARBOX_RESET_REG:DAC_RESET + localparam DAC_RESET_MSB = 1; //GEARBOX_RESET_REG:DAC_RESET + localparam DAC_RESET = 1; //GEARBOX_RESET_REG:DAC_RESET diff --git a/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh new file mode 100644 index 000000000..48401684a --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/versioning_regs_regmap_utils.vh @@ -0,0 +1,153 @@ +// +// Copyright 2021 Ettus Research, A National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: versioning_regs_regmap_utils.vh +// Description: +// The constants in this file are autogenerated by XmlParse. + +//=============================================================================== +// A numerically ordered list of registers and their HDL source files +//=============================================================================== + + // CURRENT_VERSION : 0x0 (x4xx_versioning_regs.v) + // OLDEST_COMPATIBLE_VERSION : 0x4 (x4xx_versioning_regs.v) + // VERSION_LAST_MODIFIED : 0x8 (x4xx_versioning_regs.v) + // RESERVED : 0xC (x4xx_versioning_regs.v) + +//=============================================================================== +// RegTypes +//=============================================================================== + + // RESERVED_TYPE Type (from x4xx_versioning_regs.v) + localparam RESERVED_TYPE_SIZE = 32; + localparam RESERVED_TYPE_MASK = 32'h0; + + // TIMESTAMP_TYPE Type (from x4xx_versioning_regs.v) + localparam TIMESTAMP_TYPE_SIZE = 32; + localparam TIMESTAMP_TYPE_MASK = 32'hFFFFFFFF; + localparam HH_SIZE = 8; //TIMESTAMP_TYPE:HH + localparam HH_MSB = 7; //TIMESTAMP_TYPE:HH + localparam HH = 0; //TIMESTAMP_TYPE:HH + localparam DD_SIZE = 8; //TIMESTAMP_TYPE:DD + localparam DD_MSB = 15; //TIMESTAMP_TYPE:DD + localparam DD = 8; //TIMESTAMP_TYPE:DD + localparam MM_SIZE = 8; //TIMESTAMP_TYPE:MM + localparam MM_MSB = 23; //TIMESTAMP_TYPE:MM + localparam MM = 16; //TIMESTAMP_TYPE:MM + localparam YY_SIZE = 8; //TIMESTAMP_TYPE:YY + localparam YY_MSB = 31; //TIMESTAMP_TYPE:YY + localparam YY = 24; //TIMESTAMP_TYPE:YY + + // VERSION_TYPE Type (from x4xx_versioning_regs.v) + localparam VERSION_TYPE_SIZE = 32; + localparam VERSION_TYPE_MASK = 32'hFFFFFFFF; + localparam BUILD_SIZE = 12; //VERSION_TYPE:BUILD + localparam BUILD_MSB = 11; //VERSION_TYPE:BUILD + localparam BUILD = 0; //VERSION_TYPE:BUILD + localparam MINOR_SIZE = 11; //VERSION_TYPE:MINOR + localparam MINOR_MSB = 22; //VERSION_TYPE:MINOR + localparam MINOR = 12; //VERSION_TYPE:MINOR + localparam MAJOR_SIZE = 9; //VERSION_TYPE:MAJOR + localparam MAJOR_MSB = 31; //VERSION_TYPE:MAJOR + localparam MAJOR = 23; //VERSION_TYPE:MAJOR + +//=============================================================================== +// Register Group VERSIONING_CONSTANTS +//=============================================================================== + + // Enumerated type CPLD_IFC_VERSION + localparam CPLD_IFC_VERSION_SIZE = 7; + localparam CPLD_IFC_CURRENT_VERSION_MINOR = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_CURRENT_VERSION_MINOR + localparam CPLD_IFC_CURRENT_VERSION_BUILD = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_CURRENT_VERSION_BUILD + localparam CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MINOR + localparam CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // CPLD_IFC_VERSION:CPLD_IFC_OLDEST_COMPATIBLE_VERSION_BUILD + localparam CPLD_IFC_CURRENT_VERSION_MAJOR = 'h2; // CPLD_IFC_VERSION:CPLD_IFC_CURRENT_VERSION_MAJOR + localparam CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h2; // CPLD_IFC_VERSION:CPLD_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR + localparam CPLD_IFC_VERSION_LAST_MODIFIED_TIME = 'h21011809; // CPLD_IFC_VERSION:CPLD_IFC_VERSION_LAST_MODIFIED_TIME + + // Enumerated type DB_GPIO_IFC_VERSION + localparam DB_GPIO_IFC_VERSION_SIZE = 7; + localparam DB_GPIO_IFC_CURRENT_VERSION_MINOR = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_MINOR + localparam DB_GPIO_IFC_CURRENT_VERSION_BUILD = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_BUILD + localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR + localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD + localparam DB_GPIO_IFC_CURRENT_VERSION_MAJOR = 'h1; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_CURRENT_VERSION_MAJOR + localparam DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR + localparam DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME = 'h20110616; // DB_GPIO_IFC_VERSION:DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME + + // Enumerated type FPGA_VERSION + localparam FPGA_VERSION_SIZE = 7; + localparam FPGA_CURRENT_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_CURRENT_VERSION_BUILD + localparam FPGA_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MINOR + localparam FPGA_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_BUILD + localparam FPGA_CURRENT_VERSION_MINOR = 'h3; // FPGA_VERSION:FPGA_CURRENT_VERSION_MINOR + localparam FPGA_CURRENT_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_CURRENT_VERSION_MAJOR + localparam FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h7; // FPGA_VERSION:FPGA_OLDEST_COMPATIBLE_VERSION_MAJOR + localparam FPGA_VERSION_LAST_MODIFIED_TIME = 'h21041616; // FPGA_VERSION:FPGA_VERSION_LAST_MODIFIED_TIME + + // Enumerated type RF_CORE_100M_VERSION + localparam RF_CORE_100M_VERSION_SIZE = 7; + localparam RF_CORE_100M_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_MINOR + localparam RF_CORE_100M_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_BUILD + localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MINOR + localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_BUILD + localparam RF_CORE_100M_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_100M_VERSION:RF_CORE_100M_CURRENT_VERSION_MAJOR + localparam RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_100M_VERSION:RF_CORE_100M_OLDEST_COMPATIBLE_VERSION_MAJOR + localparam RF_CORE_100M_VERSION_LAST_MODIFIED_TIME = 'h20102617; // RF_CORE_100M_VERSION:RF_CORE_100M_VERSION_LAST_MODIFIED_TIME + + // Enumerated type RF_CORE_400M_VERSION + localparam RF_CORE_400M_VERSION_SIZE = 7; + localparam RF_CORE_400M_CURRENT_VERSION_MINOR = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_MINOR + localparam RF_CORE_400M_CURRENT_VERSION_BUILD = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_BUILD + localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MINOR + localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD = 'h0; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_BUILD + localparam RF_CORE_400M_CURRENT_VERSION_MAJOR = 'h1; // RF_CORE_400M_VERSION:RF_CORE_400M_CURRENT_VERSION_MAJOR + localparam RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR = 'h1; // RF_CORE_400M_VERSION:RF_CORE_400M_OLDEST_COMPATIBLE_VERSION_MAJOR + localparam RF_CORE_400M_VERSION_LAST_MODIFIED_TIME = 'h20102617; // RF_CORE_400M_VERSION:RF_CORE_400M_VERSION_LAST_MODIFIED_TIME + +//=============================================================================== +// Register Group VERSIONING_REGS +//=============================================================================== + + // Enumerated type COMPONENTS_INDEXES + localparam COMPONENTS_INDEXES_SIZE = 6; + localparam FPGA_VERSION_INDEX = 'h0; // COMPONENTS_INDEXES:FPGA_VERSION_INDEX + localparam CPLD_IFC_INDEX = 'h1; // COMPONENTS_INDEXES:CPLD_IFC_INDEX + localparam DB0_RF_CORE_INDEX = 'h2; // COMPONENTS_INDEXES:DB0_RF_CORE_INDEX + localparam DB1_RF_CORE_INDEX = 'h3; // COMPONENTS_INDEXES:DB1_RF_CORE_INDEX + localparam DB0_GPIO_IFC_INDEX = 'h4; // COMPONENTS_INDEXES:DB0_GPIO_IFC_INDEX + localparam DB1_GPIO_IFC_INDEX = 'h5; // COMPONENTS_INDEXES:DB1_GPIO_IFC_INDEX + + // CURRENT_VERSION Register (from x4xx_versioning_regs.v) + localparam CURRENT_VERSION_COUNT = 64; // Number of elements in array + + // OLDEST_COMPATIBLE_VERSION Register (from x4xx_versioning_regs.v) + localparam OLDEST_COMPATIBLE_VERSION_COUNT = 64; // Number of elements in array + + // VERSION_LAST_MODIFIED Register (from x4xx_versioning_regs.v) + localparam VERSION_LAST_MODIFIED_COUNT = 64; // Number of elements in array + + // RESERVED Register (from x4xx_versioning_regs.v) + localparam RESERVED_COUNT = 64; // Number of elements in array + + // Return the offset of an element of register array CURRENT_VERSION + function integer CURRENT_VERSION (input integer i); + CURRENT_VERSION = (i * 'h10) + 'h0; + endfunction + + // Return the offset of an element of register array OLDEST_COMPATIBLE_VERSION + function integer OLDEST_COMPATIBLE_VERSION (input integer i); + OLDEST_COMPATIBLE_VERSION = (i * 'h10) + 'h4; + endfunction + + // Return the offset of an element of register array VERSION_LAST_MODIFIED + function integer VERSION_LAST_MODIFIED (input integer i); + VERSION_LAST_MODIFIED = (i * 'h10) + 'h8; + endfunction + + // Return the offset of an element of register array RESERVED + function integer RESERVED (input integer i); + RESERVED = (i * 'h10) + 'hC; + endfunction diff --git a/fpga/usrp3/top/x400/regmap/versioning_utils.vh b/fpga/usrp3/top/x400/regmap/versioning_utils.vh new file mode 100644 index 000000000..9ef188997 --- /dev/null +++ b/fpga/usrp3/top/x400/regmap/versioning_utils.vh @@ -0,0 +1,109 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: versioning_utils +// +// Description: +// +// Contains constants and functions for versioning purposes +// +// IMPORTANT! The constants and functions defined in this file depend +// on versioning_regs_regmap_utils.vh, which must be +// included before this file. +// + + +// Each component consists of 3 x 32-bit values (96-bit total) +// The component's versions are located in the flat component's +// version vector as shown below, following the same order in which +// the registers' offsets are implemented. +// +// Version element Bit ranges 32-bit word position +// Current version [31: 0] 0 +// Oldest compatible version [63:32] 1 +// Last modified [95:64] 2 + +localparam COMPONENT_VERSIONS_SIZE = + TIMESTAMP_TYPE_SIZE + VERSION_TYPE_SIZE + VERSION_TYPE_SIZE; // 96 + +// There are up to 64 addressable components' versions in the +// versioning module's version_info input vector. +localparam MAX_NUM_OF_COMPONENTS = 64; + +// Define constants for each field's LSB in the flat vector. +// Start bit = 8-bit * (register offset with index 0) +localparam CURRENT_VERSION_LSB = 8 * CURRENT_VERSION(0); // 0 +localparam OLDEST_COMPATIBLE_VERSION_LSB = 8 * OLDEST_COMPATIBLE_VERSION(0); // 32 +localparam TIMESTAMP_LSB = 8 * VERSION_LAST_MODIFIED(0); // 64 + +// This function takes the major, minor and build values for the current +// version field, and returns a vector of size VERSION_TYPE_SIZE +// that contains those fields at the proper location. +function automatic [VERSION_TYPE_SIZE-1:0] build_version; + input [MAJOR_SIZE-1:0] major; + input [MINOR_SIZE-1:0] minor; + input [BUILD_SIZE-1:0] build; +begin + build_version[MAJOR+:MAJOR_SIZE] = major; + build_version[MINOR+:MINOR_SIZE] = minor; + build_version[BUILD+:BUILD_SIZE] = build; +end +endfunction + +// This function takes the 3 versioning fields that comprise a component's +// version (current, oldest compatible, timestamp), and concatenates them +// in the expected order (see details above). +// The function returns a vector of size COMPONENT_VERSIONS_SIZE with +// all the component's versions. +function automatic [COMPONENT_VERSIONS_SIZE-1:0] build_component_versions; + input [TIMESTAMP_TYPE_SIZE-1:0] timestamp; + input [VERSION_TYPE_SIZE-1:0] oldest_compatible_version; + input [VERSION_TYPE_SIZE-1:0] current_version; +begin + // Current version mapping + build_component_versions[CURRENT_VERSION_LSB +: VERSION_TYPE_SIZE] = current_version; + // Oldest compatible version mapping + build_component_versions[OLDEST_COMPATIBLE_VERSION_LSB +: VERSION_TYPE_SIZE] = oldest_compatible_version; + // Last modified + build_component_versions[TIMESTAMP_LSB +: TIMESTAMP_TYPE_SIZE] = timestamp; +end +endfunction + +// This function retrieves a component's version information, based on the +// provided index, from the vector containing all the components' versions. +function automatic [COMPONENT_VERSIONS_SIZE-1:0] get_component_versions; + input [MAX_NUM_OF_COMPONENTS*COMPONENT_VERSIONS_SIZE-1:0] version_info_vector; + input integer component_index; +begin + get_component_versions = version_info_vector[COMPONENT_VERSIONS_SIZE*component_index +: COMPONENT_VERSIONS_SIZE]; +end +endfunction + +// This function takes a component's version info and returns the +// current version field. +function automatic [VERSION_TYPE_SIZE-1:0] current_version; + input [COMPONENT_VERSIONS_SIZE-1:0] component_versions; +begin + current_version = component_versions[CURRENT_VERSION_LSB +: VERSION_TYPE_SIZE]; +end +endfunction + +// This function takes a component's version info and returns the +// oldest compatible version field. +function automatic [VERSION_TYPE_SIZE-1:0] oldest_compatible_version; + input [COMPONENT_VERSIONS_SIZE-1:0] component_versions; +begin + oldest_compatible_version = component_versions[OLDEST_COMPATIBLE_VERSION_LSB +: VERSION_TYPE_SIZE]; +end +endfunction + +// This function takes a component's version info and returns the +// version last modified field. +function automatic [VERSION_TYPE_SIZE-1:0] version_last_modified; + input [COMPONENT_VERSIONS_SIZE-1:0] component_versions; +begin + version_last_modified = component_versions[TIMESTAMP_LSB +: TIMESTAMP_TYPE_SIZE]; +end +endfunction |