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-rw-r--r--usrp2/coregen/Makefile.srcs4
-rw-r--r--usrp2/coregen/coregen.cgp22
-rw-r--r--usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v6
-rw-r--r--usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco6
-rw-r--r--usrp2/extramfifo/ext_fifo.v76
-rw-r--r--usrp2/extramfifo/ext_fifo_tb.v36
-rw-r--r--usrp2/extramfifo/icon.v1286
-rw-r--r--usrp2/extramfifo/icon.xco47
-rw-r--r--usrp2/extramfifo/ila.v5544
-rw-r--r--usrp2/extramfifo/ila.xco130
-rw-r--r--usrp2/extramfifo/nobl_fifo.v20
-rw-r--r--usrp2/extramfifo/nobl_if.v9
-rw-r--r--usrp2/extramfifo/test_sram_if.v4
-rw-r--r--usrp2/fifo/fifo_cascade.v8
-rw-r--r--usrp2/top/Makefile.common1
-rw-r--r--usrp2/top/u2_rev3/Makefile.udp2
-rw-r--r--usrp2/top/u2_rev3/u2_core_udp.v57
-rw-r--r--usrp2/top/u2_rev3/u2_rev3.ucf86
-rw-r--r--usrp2/top/u2_rev3/u2_rev3.v221
19 files changed, 7327 insertions, 238 deletions
diff --git a/usrp2/coregen/Makefile.srcs b/usrp2/coregen/Makefile.srcs
index 7b29225ca..a59696d15 100644
--- a/usrp2/coregen/Makefile.srcs
+++ b/usrp2/coregen/Makefile.srcs
@@ -16,4 +16,8 @@ fifo_xlnx_16x19_2clk.v \
fifo_xlnx_16x19_2clk.xco \
fifo_xlnx_16x40_2clk.v \
fifo_xlnx_16x40_2clk.xco \
+fifo_xlnx_512x36_2clk_36to18.v \
+fifo_xlnx_512x36_2clk_36to18.xco \
+fifo_xlnx_512x36_2clk_18to36.v \
+fifo_xlnx_512x36_2clk_18to36.xco \
))
diff --git a/usrp2/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp
index 810d64dac..4c9201aff 100644
--- a/usrp2/coregen/coregen.cgp
+++ b/usrp2/coregen/coregen.cgp
@@ -1,20 +1,22 @@
-# Date: Thu Sep 3 17:40:48 2009
-SET addpads = False
-SET asysymbol = False
+# Date: Mon Jul 26 21:55:33 2010
+
+SET addpads = false
+SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
+SET createndf = false
SET designentry = Verilog
SET device = xc3s2000
SET devicefamily = spartan3
SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
+SET formalverification = false
+SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fg456
-SET removerpms = False
+SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -5
-SET verilogsim = True
-SET vhdlsim = False
-SET workingdirectory = /home/matt/coregen/tmp
+SET verilogsim = true
+SET vhdlsim = false
+SET workingdirectory = /tmp/
+# CRC: 394da717
diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
index 1d7a5ca2a..32de19e8a 100644
--- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v
@@ -44,6 +44,7 @@ module fifo_xlnx_512x36_2clk_18to36(
rst,
wr_clk,
wr_en,
+ almost_full,
dout,
empty,
full);
@@ -55,6 +56,7 @@ input rd_en;
input rst;
input wr_clk;
input wr_en;
+output almost_full;
output [35 : 0] dout;
output empty;
output full;
@@ -73,7 +75,7 @@ output full;
.C_FAMILY("spartan3"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
- .C_HAS_ALMOST_FULL(0),
+ .C_HAS_ALMOST_FULL(1),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
@@ -128,6 +130,7 @@ output full;
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
+ .ALMOST_FULL(almost_full),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
@@ -145,7 +148,6 @@ output full;
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
- .ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
diff --git a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
index df97fd0e0..05ceffbe9 100644
--- a/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
+++ b/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.xco
@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version K.39
-# Date: Thu Jul 29 23:02:41 2010
+# Date: Fri Jul 30 20:43:00 2010
#
##############################################################
#
@@ -36,7 +36,7 @@ SELECT Fifo_Generator family Xilinx,_Inc. 4.4
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
-CSET almost_full_flag=false
+CSET almost_full_flag=true
CSET component_name=fifo_xlnx_512x36_2clk_18to36
CSET data_count=false
CSET data_count_width=10
@@ -78,5 +78,5 @@ CSET write_data_count=false
CSET write_data_count_width=10
# END Parameters
GENERATE
-# CRC: 117ae77f
+# CRC: 9b689ee4
diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v
index 55935146a..a506d71e2 100644
--- a/usrp2/extramfifo/ext_fifo.v
+++ b/usrp2/extramfifo/ext_fifo.v
@@ -1,3 +1,20 @@
+//
+// FIFO backed by an off chip ZBT/NoBL SRAM.
+//
+// This module and its sub-hierarchy implment a FIFO capable of sustaining
+// a data throughput rate of at least int_clk/2 * 36bits and bursts of int_clk * 36bits.
+//
+// This has been designed and tested for an int_clk of 100MHz and an ext_clk of 125MHz,
+// your milage may vary with other clock ratio's especially those where int_clk < ext_clk.
+// Testing has also exclusively used a rst signal synchronized to int_clk.
+//
+// Interface operation mimics a Xilinx FIFO configured as "First Word Fall Through",
+// though signal naming differs.
+//
+// For FPGA use registers interfacing directly with signals prefixed "RAM_*" should be
+// packed into the IO ring.
+//
+
module ext_fifo
#(parameter INT_WIDTH=36,EXT_WIDTH=18,DEPTH=19)
(
@@ -24,25 +41,24 @@ module ext_fifo
wire [EXT_WIDTH-1:0] write_data;
wire [EXT_WIDTH-1:0] read_data;
wire full1, empty1;
- wire full2, empty2;
-
+ wire almost_full2, full2, empty2;
+ wire [INT_WIDTH-1:0] data_to_fifo;
+ wire [INT_WIDTH-1:0] data_from_fifo;
+
// FIFO buffers data from UDP engine into external FIFO clock domain.
fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 (
.rst(rst),
.wr_clk(int_clk),
.rd_clk(ext_clk),
- .din(datain), // Bus [35 : 0]
- .wr_en(src_rdy_i),
- .rd_en(space_avail&~empty1),
- // .rd_en(~full2&~empty1),
+ .din(datain), // Bus [35 : 0]
+ .wr_en(src_rdy_i),
+ .rd_en(space_avail&~empty1),
.dout(write_data), // Bus [17 : 0]
.full(full1),
.empty(empty1));
assign dst_rdy_o = ~full1;
-
-
// External FIFO running at ext clock rate and 18 bit width.
nobl_fifo #(.WIDTH(EXT_WIDTH),.DEPTH(DEPTH))
nobl_fifo_i1
@@ -63,10 +79,10 @@ module ext_fifo
.space_avail(space_avail),
.read_data(read_data),
.read_strobe(data_avail & ~full2),
- .data_avail(data_avail)
+ .data_avail(data_avail),
+ .upstream_full(almost_full2)
);
-
-
+
// FIFO buffers data read from external FIFO into DSP clk domain and to TX DSP.
fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36_i1 (
@@ -74,47 +90,13 @@ module ext_fifo
.wr_clk(ext_clk),
.rd_clk(int_clk),
.din(read_data), // Bus [17 : 0]
- // .din(write_data), // Bus [17 : 0]
.wr_en(data_avail & ~full2 ),
- // .wr_en(~full2&~empty1),
.rd_en(dst_rdy_i),
- .dout(dataout), // Bus [35 : 0]
+ .dout(dataout), // Bus [35 : 0]
.full(full2),
+ .almost_full(almost_full2),
.empty(empty2));
assign src_rdy_o = ~empty2;
-
- wire [35:0] CONTROL0;
- reg [7:0] datain_reg,write_data_reg,read_data_reg ;
- reg space_avail_reg,data_avail_reg,empty1_reg,full2_reg ;
-
- always @(posedge ext_clk)
- begin
- //datain_reg <= datain[7:0];
- write_data_reg <= write_data[7:0];
- read_data_reg <= read_data[7:0];
- space_avail_reg <= space_avail;
- data_avail_reg <= data_avail;
- empty1_reg <= empty1;
- full2_reg <= full2;
- end
-
-
- icon icon_i1
- (
- .CONTROL0(CONTROL0)
- );
-
- ila ila_i1
- (
- .CLK(ext_clk),
- .CONTROL(CONTROL0),
- // .TRIG0(address_reg),
- .TRIG0(write_data_reg[7:0]),
- .TRIG1(read_data_reg[7:0]),
- .TRIG2(0),
- .TRIG3({space_avail_reg,data_avail_reg,empty1_reg,full2_reg})
- );
-
endmodule // ext_fifo
diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v
index aa1fd6e3c..38df4a285 100644
--- a/usrp2/extramfifo/ext_fifo_tb.v
+++ b/usrp2/extramfifo/ext_fifo_tb.v
@@ -58,18 +58,18 @@ module ext_fifo_tb();
repeat (5) @(negedge int_clk);
rst <= 0;
@(negedge int_clk);
- repeat (1000)
+ repeat (4000)
begin
@(negedge int_clk);
- datain <= datain + 1;
- src_rdy_i <= 1;
- @(negedge int_clk);
- src_rdy_i <= 0;
+ datain <= datain + dst_rdy_o;
+ src_rdy_i <= dst_rdy_o;
+// @(negedge int_clk);
+// src_rdy_i <= 0;
// @(negedge int_clk);
// dst_rdy_i <= src_rdy_o;
// @(negedge int_clk);
// dst_rdy_i <= 0;
- repeat (2) @(negedge int_clk);
+// repeat (2) @(negedge int_clk);
end // repeat (1000)
// Fall through fifo, first output already valid
if (dataout !== ref_dataout)
@@ -77,16 +77,16 @@ module ext_fifo_tb();
repeat (1000)
begin
@(negedge int_clk);
- datain <= datain + 1;
- src_rdy_i <= 1;
+ datain <= datain + dst_rdy_o ;
+ src_rdy_i <= dst_rdy_o;
@(negedge int_clk);
src_rdy_i <= 0;
@(negedge int_clk);
- ref_dataout <= ref_dataout + 1;
+ ref_dataout <= ref_dataout + src_rdy_o ;
dst_rdy_i <= src_rdy_o;
- @(negedge int_clk);
- if (dataout !== ref_dataout)
+ if ((dataout !== ref_dataout) && src_rdy_o)
$display("Error: Expected %x, got %x",ref_dataout, dataout);
+ @(negedge int_clk);
dst_rdy_i <= 0;
// repeat (2) @(negedge int_clk);
end // repeat (1000)
@@ -98,11 +98,11 @@ module ext_fifo_tb();
// @(negedge int_clk);
// src_rdy_i <= 0;
@(negedge int_clk);
- ref_dataout <= ref_dataout + 1;
+ ref_dataout <= ref_dataout + src_rdy_o;
dst_rdy_i <= src_rdy_o;
- @(negedge int_clk);
- if (dataout !== ref_dataout)
+ if ((dataout !== ref_dataout) && src_rdy_o)
$display("Error: Expected %x, got %x",ref_dataout, dataout);
+ @(negedge int_clk);
dst_rdy_i <= 0;
// repeat (2) @(negedge int_clk);
end // repeat (1000)
@@ -210,13 +210,7 @@ module ext_fifo_tb();
assign #2 RAM_A_ext = RAM_A;
-/* -----\/----- EXCLUDED -----\/-----
- wire [13:0] temp1;
- assign temp1 = 14'h0;
- wire [3:0] temp2;
- assign temp2 = 4'h0;
- -----/\----- EXCLUDED -----/\----- */
-
+
idt71v65603s150 idt71v65603s150_i1
(
diff --git a/usrp2/extramfifo/icon.v b/usrp2/extramfifo/icon.v
new file mode 100644
index 000000000..6537e9340
--- /dev/null
+++ b/usrp2/extramfifo/icon.v
@@ -0,0 +1,1286 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: M.53d
+// \ \ Application: netgen
+// / / Filename: icon.v
+// /___/ /\ Timestamp: Tue Jul 20 20:31:15 2010
+// \ \ / \
+// \___\/\___\
+//
+// Command : -w -sim -ofmt verilog /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.ngc /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.v
+// Device : xc3s2000-fg456-5
+// Input file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.ngc
+// Output file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/icon.v
+// # of Modules : 1
+// Design Name : icon
+// Xilinx : /opt/Xilinx/12.1/ISE_DS/ISE
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module icon (
+CONTROL0
+)/* synthesis syn_black_box syn_noprune=1 */;
+ inout [35 : 0] CONTROL0;
+
+ // synthesis translate_off
+
+ wire N1;
+ wire \U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ;
+ wire \U0/U_ICON/U_CMD/iSEL_n ;
+ wire \U0/U_ICON/U_CMD/iTARGET_CE ;
+ wire \U0/U_ICON/U_CTRL_OUT/iDATA_VALID ;
+ wire \U0/U_ICON/U_STAT/iCMD_GRP0_SEL ;
+ wire \U0/U_ICON/U_STAT/iDATA_VALID ;
+ wire \U0/U_ICON/U_STAT/iSTATCMD_CE ;
+ wire \U0/U_ICON/U_STAT/iSTATCMD_CE_n ;
+ wire \U0/U_ICON/U_STAT/iSTAT_HIGH ;
+ wire \U0/U_ICON/U_STAT/iSTAT_LOW ;
+ wire \U0/U_ICON/U_STAT/iTDO_next ;
+ wire \U0/U_ICON/U_SYNC/iDATA_CMD_n ;
+ wire \U0/U_ICON/U_SYNC/iGOT_SYNC ;
+ wire \U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ;
+ wire \U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ;
+ wire \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ;
+ wire \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ;
+ wire \U0/U_ICON/iCORE_ID_SEL[0] ;
+ wire \U0/U_ICON/iCORE_ID_SEL[15] ;
+ wire \U0/U_ICON/iDATA_CMD ;
+ wire \U0/U_ICON/iDATA_CMD_n ;
+ wire \U0/U_ICON/iSEL ;
+ wire \U0/U_ICON/iSEL_n ;
+ wire \U0/U_ICON/iSYNC ;
+ wire \U0/U_ICON/iTDI ;
+ wire \U0/U_ICON/iTDO ;
+ wire \U0/U_ICON/iTDO_next ;
+ wire \U0/iSHIFT_OUT ;
+ wire \U0/iUPDATE_OUT ;
+ wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_DRCK2_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_RESET_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_CAPTURE_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_SEL2_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT_O_UNCONNECTED ;
+ wire \NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT_O_UNCONNECTED ;
+ wire [11 : 8] \U0/U_ICON/U_CMD/iTARGET ;
+ wire [1 : 0] \U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL ;
+ wire [5 : 1] \U0/U_ICON/U_STAT/U_STAT_CNT/CI ;
+ wire [5 : 0] \U0/U_ICON/U_STAT/U_STAT_CNT/D ;
+ wire [5 : 0] \U0/U_ICON/U_STAT/U_STAT_CNT/S ;
+ wire [3 : 0] \U0/U_ICON/U_STAT/iSTAT ;
+ wire [5 : 0] \U0/U_ICON/U_STAT/iSTAT_CNT ;
+ wire [6 : 0] \U0/U_ICON/U_SYNC/iSYNC_WORD ;
+ wire [1 : 0] \U0/U_ICON/iCOMMAND_GRP ;
+ wire [15 : 0] \U0/U_ICON/iCOMMAND_SEL ;
+ wire [3 : 0] \U0/U_ICON/iCORE_ID ;
+ wire [15 : 15] \U0/U_ICON/iTDO_VEC ;
+ GND XST_GND (
+ .G(CONTROL0[2])
+ );
+ VCC XST_VCC (
+ .P(N1)
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_TDI_reg (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/iTDI ),
+ .Q(CONTROL0[1])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_TDO_reg (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/iTDO_next ),
+ .Q(\U0/U_ICON/iTDO )
+ );
+ FDC #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_iDATA_CMD (
+ .C(\U0/iUPDATE_OUT ),
+ .CLR(\U0/U_ICON/iSEL_n ),
+ .D(\U0/U_ICON/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/iDATA_CMD )
+ );
+ MUXF5 \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_2_f5 (
+ .I0(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 ),
+ .I1(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 ),
+ .S(\U0/U_ICON/iCORE_ID [3]),
+ .O(\U0/U_ICON/iTDO_next )
+ );
+ LUT4 #(
+ .INIT ( 16'h0002 ))
+ \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4 (
+ .I0(CONTROL0[3]),
+ .I1(\U0/U_ICON/iCORE_ID [0]),
+ .I2(\U0/U_ICON/iCORE_ID [1]),
+ .I3(\U0/U_ICON/iCORE_ID [2]),
+ .O(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_4_92 )
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3 (
+ .I0(\U0/U_ICON/iTDO_VEC [15]),
+ .I1(\U0/U_ICON/iCORE_ID [0]),
+ .I2(\U0/U_ICON/iCORE_ID [1]),
+ .I3(\U0/U_ICON/iCORE_ID [2]),
+ .O(\U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O_3_91 )
+ );
+ INV \U0/U_ICON/U_iSEL_n (
+ .I(\U0/U_ICON/iSEL ),
+ .O(\U0/U_ICON/iSEL_n )
+ );
+ INV \U0/U_ICON/U_iDATA_CMD_n (
+ .I(\U0/U_ICON/iDATA_CMD ),
+ .O(\U0/U_ICON/iDATA_CMD_n )
+ );
+ BSCAN_SPARTAN3 \U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS (
+ .TDI(\U0/U_ICON/iTDI ),
+ .SHIFT(\U0/iSHIFT_OUT ),
+ .DRCK1(\U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ),
+ .DRCK2(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_DRCK2_UNCONNECTED ),
+ .RESET(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_RESET_UNCONNECTED ),
+ .UPDATE(\U0/iUPDATE_OUT ),
+ .TDO1(\U0/U_ICON/iTDO ),
+ .TDO2(CONTROL0[2]),
+ .CAPTURE(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_CAPTURE_UNCONNECTED ),
+ .SEL1(\U0/U_ICON/iSEL ),
+ .SEL2(\NLW_U0/U_ICON/I_YES_BSCAN.U_BS/I_SPARTAN3.ISYN.I_USE_SOFTBSCAN_EQ0.I_3.U_BS_SEL2_UNCONNECTED )
+ );
+ icon_bscan_bufg \U0/U_ICON/I_YES_BSCAN.U_BS/I_USE_SOFTBSCAN_EQ0.I_USE_XST_TCK_WORKAROUND_EQ1.U_ICON_BSCAN_BUFG (
+ .DRCK_LOCAL_I(\U0/U_ICON/I_YES_BSCAN.U_BS/DRCK1 ),
+ .DRCK_LOCAL_O(CONTROL0[0])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/U_ICON/U_SYNC/U_GOT_SYNC (
+ .I0(\U0/U_ICON/U_SYNC/iGOT_SYNC_LOW ),
+ .I1(\U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH ),
+ .O(\U0/U_ICON/U_SYNC/iGOT_SYNC )
+ );
+ LUT4 #(
+ .INIT ( 16'h0200 ))
+ \U0/U_ICON/U_SYNC/U_GOT_SYNC_L (
+ .I0(\U0/U_ICON/U_SYNC/iSYNC_WORD [0]),
+ .I1(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]),
+ .I2(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]),
+ .I3(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]),
+ .O(\U0/U_ICON/U_SYNC/iGOT_SYNC_LOW )
+ );
+ LUT4 #(
+ .INIT ( 16'h0400 ))
+ \U0/U_ICON/U_SYNC/U_GOT_SYNC_H (
+ .I0(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]),
+ .I1(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]),
+ .I2(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]),
+ .I3(CONTROL0[1]),
+ .O(\U0/U_ICON/U_SYNC/iGOT_SYNC_HIGH )
+ );
+ INV \U0/U_ICON/U_SYNC/U_iDATA_CMD_n (
+ .I(\U0/U_ICON/iDATA_CMD ),
+ .O(\U0/U_ICON/U_SYNC/iDATA_CMD_n )
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/U_SYNC (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_SYNC/iGOT_SYNC ),
+ .D(N1),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/iSYNC )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[0].I_NE0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [1]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [0])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[1].I_NE0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [2]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [1])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[2].I_NE0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [3]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [2])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[3].I_NE0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [4]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [3])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [5]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [4])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(\U0/U_ICON/U_SYNC/iSYNC_WORD [6]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [5])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_SYNC/G_SYNC_WORD[6].I_EQ0.U_FDR (
+ .C(CONTROL0[0]),
+ .D(CONTROL0[1]),
+ .R(\U0/U_ICON/U_SYNC/iDATA_CMD_n ),
+ .Q(\U0/U_ICON/U_SYNC/iSYNC_WORD [6])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[0].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [0]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[20])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[0].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [0]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[4])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [1]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[21])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [1]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[5])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [2]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[22])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[2].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [2]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[6])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [3]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[23])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[3].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [3]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[7])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [4]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[24])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[4].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [4]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[8])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [5]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[25])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[5].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [5]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[9])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [6]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[26])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[6].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [6]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[10])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [7]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[27])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[7].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [7]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[11])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [8]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[28])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [8]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[12])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [9]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[29])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [9]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[13])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [10]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[30])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[10].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [10]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[14])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [11]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[31])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[11].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [11]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[15])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [12]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[32])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[12].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [12]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[16])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [13]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[33])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[13].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [13]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[17])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [14]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[34])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[14].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [14]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[18])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_HCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [15]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1]),
+ .O(CONTROL0[35])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE (
+ .I0(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [15]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[0] ),
+ .I3(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0]),
+ .O(CONTROL0[19])
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \U0/U_ICON/U_CTRL_OUT/U_CMDGRP1 (
+ .I0(\U0/U_ICON/iCOMMAND_GRP [0]),
+ .I1(\U0/U_ICON/iCOMMAND_GRP [1]),
+ .O(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [1])
+ );
+ LUT2 #(
+ .INIT ( 4'h1 ))
+ \U0/U_ICON/U_CTRL_OUT/U_CMDGRP0 (
+ .I0(\U0/U_ICON/iCOMMAND_GRP [0]),
+ .I1(\U0/U_ICON/iCOMMAND_GRP [1]),
+ .O(\U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL [0])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/U_ICON/U_CTRL_OUT/U_DATA_VALID (
+ .I0(\U0/U_ICON/iSYNC ),
+ .I1(\U0/iSHIFT_OUT ),
+ .O(\U0/U_ICON/U_CTRL_OUT/iDATA_VALID )
+ );
+ LUT4 #(
+ .INIT ( 16'h0001 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\U0/U_ICON/iCORE_ID_SEL[0] )
+ );
+ LUT4 #(
+ .INIT ( 16'h0002 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[1].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0004 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[2].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0008 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[3].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0010 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[4].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0020 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[5].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0040 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[6].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0080 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[7].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0100 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[8].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0200 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[9].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0400 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[10].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0800 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[11].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h1000 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[12].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h2000 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[13].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h4000 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\NLW_U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[14].U_LUT_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[15].U_LUT (
+ .I0(\U0/U_ICON/iCORE_ID [0]),
+ .I1(\U0/U_ICON/iCORE_ID [1]),
+ .I2(\U0/U_ICON/iCORE_ID [2]),
+ .I3(\U0/U_ICON/iCORE_ID [3]),
+ .O(\U0/U_ICON/iCORE_ID_SEL[15] )
+ );
+ LUT4 #(
+ .INIT ( 16'h0001 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[0].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [0])
+ );
+ LUT4 #(
+ .INIT ( 16'h0002 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[1].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [1])
+ );
+ LUT4 #(
+ .INIT ( 16'h0004 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[2].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [2])
+ );
+ LUT4 #(
+ .INIT ( 16'h0008 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[3].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [3])
+ );
+ LUT4 #(
+ .INIT ( 16'h0010 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[4].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [4])
+ );
+ LUT4 #(
+ .INIT ( 16'h0020 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[5].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [5])
+ );
+ LUT4 #(
+ .INIT ( 16'h0040 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[6].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [6])
+ );
+ LUT4 #(
+ .INIT ( 16'h0080 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[7].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [7])
+ );
+ LUT4 #(
+ .INIT ( 16'h0100 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[8].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [8])
+ );
+ LUT4 #(
+ .INIT ( 16'h0200 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[9].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [9])
+ );
+ LUT4 #(
+ .INIT ( 16'h0400 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[10].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [10])
+ );
+ LUT4 #(
+ .INIT ( 16'h0800 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[11].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [11])
+ );
+ LUT4 #(
+ .INIT ( 16'h1000 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[12].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [12])
+ );
+ LUT4 #(
+ .INIT ( 16'h2000 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[13].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [13])
+ );
+ LUT4 #(
+ .INIT ( 16'h4000 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[14].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [14])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[15].U_LUT (
+ .I0(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .I1(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .I2(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .I3(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .O(\U0/U_ICON/iCOMMAND_SEL [15])
+ );
+ LUT2 #(
+ .INIT ( 4'h4 ))
+ \U0/U_ICON/U_CMD/U_TARGET_CE (
+ .I0(\U0/U_ICON/iDATA_CMD ),
+ .I1(\U0/iSHIFT_OUT ),
+ .O(\U0/U_ICON/U_CMD/iTARGET_CE )
+ );
+ INV \U0/U_ICON/U_CMD/U_SEL_n (
+ .I(\U0/U_ICON/iSEL ),
+ .O(\U0/U_ICON/U_CMD/iSEL_n )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[6].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/iCOMMAND_GRP [1]),
+ .Q(\U0/U_ICON/iCOMMAND_GRP [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[7].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/U_CMD/iTARGET [8]),
+ .Q(\U0/U_ICON/iCOMMAND_GRP [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[8].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/U_CMD/iTARGET [9]),
+ .Q(\U0/U_ICON/U_CMD/iTARGET [8])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/U_CMD/iTARGET [10]),
+ .Q(\U0/U_ICON/U_CMD/iTARGET [9])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/U_CMD/iTARGET [11]),
+ .Q(\U0/U_ICON/U_CMD/iTARGET [10])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/iCORE_ID [0]),
+ .Q(\U0/U_ICON/U_CMD/iTARGET [11])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/iCORE_ID [1]),
+ .Q(\U0/U_ICON/iCORE_ID [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[13].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/iCORE_ID [2]),
+ .Q(\U0/U_ICON/iCORE_ID [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(\U0/U_ICON/iCORE_ID [3]),
+ .Q(\U0/U_ICON/iCORE_ID [2])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET (
+ .C(CONTROL0[0]),
+ .CE(\U0/U_ICON/U_CMD/iTARGET_CE ),
+ .CLR(\U0/U_ICON/U_CMD/iSEL_n ),
+ .D(CONTROL0[1]),
+ .Q(\U0/U_ICON/iCORE_ID [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_FDRE (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [5]),
+ .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [5])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_FDRE (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [4]),
+ .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [4])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_FDRE (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [3]),
+ .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_FDRE (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [2]),
+ .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [2])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_FDRE (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [1]),
+ .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_FDRE (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/U_STAT_CNT/D [0]),
+ .R(\U0/U_ICON/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/U_ICON/U_STAT/iSTAT_CNT [0])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_LUT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [5])
+ );
+ XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[5].U_XORCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [5]),
+ .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [5]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [5])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_LUT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [4]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4])
+ );
+ MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].GnH.U_MUXCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]),
+ .DI(CONTROL0[2]),
+ .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]),
+ .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [5])
+ );
+ XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[4].U_XORCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4]),
+ .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [4]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [4])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_LUT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3])
+ );
+ MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].GnH.U_MUXCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]),
+ .DI(CONTROL0[2]),
+ .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]),
+ .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [4])
+ );
+ XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[3].U_XORCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3]),
+ .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [3]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [3])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_LUT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [2]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2])
+ );
+ MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].GnH.U_MUXCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]),
+ .DI(CONTROL0[2]),
+ .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]),
+ .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [3])
+ );
+ XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[2].U_XORCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2]),
+ .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [2]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [2])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_LUT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [1]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1])
+ );
+ MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].GnH.U_MUXCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]),
+ .DI(CONTROL0[2]),
+ .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]),
+ .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [2])
+ );
+ XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[1].U_XORCY (
+ .CI(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1]),
+ .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [1]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [1])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_LUT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0])
+ );
+ MUXCY_L \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].GnH.U_MUXCY (
+ .CI(N1),
+ .DI(CONTROL0[2]),
+ .S(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]),
+ .LO(\U0/U_ICON/U_STAT/U_STAT_CNT/CI [1])
+ );
+ XORCY \U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_XORCY (
+ .CI(N1),
+ .LI(\U0/U_ICON/U_STAT/U_STAT_CNT/S [0]),
+ .O(\U0/U_ICON/U_STAT/U_STAT_CNT/D [0])
+ );
+ MUXF6 \U0/U_ICON/U_STAT/U_TDO_next (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_LOW ),
+ .I1(\U0/U_ICON/U_STAT/iSTAT_HIGH ),
+ .S(\U0/U_ICON/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/U_ICON/U_STAT/iTDO_next )
+ );
+ MUXF5 \U0/U_ICON/U_STAT/U_STAT_LOW (
+ .I0(\U0/U_ICON/U_STAT/iSTAT [0]),
+ .I1(\U0/U_ICON/U_STAT/iSTAT [1]),
+ .S(\U0/U_ICON/U_STAT/iSTAT_CNT [4]),
+ .O(\U0/U_ICON/U_STAT/iSTAT_LOW )
+ );
+ MUXF5 \U0/U_ICON/U_STAT/U_STAT_HIGH (
+ .I0(\U0/U_ICON/U_STAT/iSTAT [2]),
+ .I1(\U0/U_ICON/U_STAT/iSTAT [3]),
+ .S(\U0/U_ICON/U_STAT/iSTAT_CNT [4]),
+ .O(\U0/U_ICON/U_STAT/iSTAT_HIGH )
+ );
+ LUT4 #(
+ .INIT ( 16'h0101 ))
+ \U0/U_ICON/U_STAT/F_STAT[0].U_STAT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/U_ICON/U_STAT/iSTAT [0])
+ );
+ LUT4 #(
+ .INIT ( 16'hC101 ))
+ \U0/U_ICON/U_STAT/F_STAT[1].U_STAT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/U_ICON/U_STAT/iSTAT [1])
+ );
+ LUT4 #(
+ .INIT ( 16'h2100 ))
+ \U0/U_ICON/U_STAT/F_STAT[2].U_STAT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/U_ICON/U_STAT/iSTAT [2])
+ );
+ LUT4 #(
+ .INIT ( 16'h1610 ))
+ \U0/U_ICON/U_STAT/F_STAT[3].U_STAT (
+ .I0(\U0/U_ICON/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/U_ICON/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/U_ICON/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/U_ICON/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/U_ICON/U_STAT/iSTAT [3])
+ );
+ INV \U0/U_ICON/U_STAT/U_STATCMD_n (
+ .I(\U0/U_ICON/U_STAT/iSTATCMD_CE ),
+ .O(\U0/U_ICON/U_STAT/iSTATCMD_CE_n )
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_ICON/U_STAT/U_STATCMD (
+ .I0(\U0/U_ICON/U_STAT/iDATA_VALID ),
+ .I1(\U0/U_ICON/iCOMMAND_SEL [0]),
+ .I2(\U0/U_ICON/iCORE_ID_SEL[15] ),
+ .I3(\U0/U_ICON/U_STAT/iCMD_GRP0_SEL ),
+ .O(\U0/U_ICON/U_STAT/iSTATCMD_CE )
+ );
+ LUT2 #(
+ .INIT ( 4'h1 ))
+ \U0/U_ICON/U_STAT/U_CMDGRP0 (
+ .I0(\U0/U_ICON/iCOMMAND_GRP [0]),
+ .I1(\U0/U_ICON/iCOMMAND_GRP [1]),
+ .O(\U0/U_ICON/U_STAT/iCMD_GRP0_SEL )
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/U_ICON/U_STAT/U_DATA_VALID (
+ .I0(\U0/U_ICON/iSYNC ),
+ .I1(\U0/iSHIFT_OUT ),
+ .O(\U0/U_ICON/U_STAT/iDATA_VALID )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/U_ICON/U_STAT/U_TDO (
+ .C(CONTROL0[0]),
+ .CE(N1),
+ .D(\U0/U_ICON/U_STAT/iTDO_next ),
+ .Q(\U0/U_ICON/iTDO_VEC [15])
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
diff --git a/usrp2/extramfifo/icon.xco b/usrp2/extramfifo/icon.xco
new file mode 100644
index 000000000..fda273149
--- /dev/null
+++ b/usrp2/extramfifo/icon.xco
@@ -0,0 +1,47 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.1
+# Date: Wed Jul 21 03:31:19 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
+# END Select
+# BEGIN Parameters
+CSET component_name=icon
+CSET enable_jtag_bufg=true
+CSET number_control_ports=1
+CSET use_ext_bscan=false
+CSET use_softbscan=false
+CSET use_unused_bscan=false
+CSET user_scan_chain=USER1
+# END Parameters
+GENERATE
+# CRC: 799ba5a1
diff --git a/usrp2/extramfifo/ila.v b/usrp2/extramfifo/ila.v
new file mode 100644
index 000000000..b0d8f8d0c
--- /dev/null
+++ b/usrp2/extramfifo/ila.v
@@ -0,0 +1,5544 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version: M.53d
+// \ \ Application: netgen
+// / / Filename: ila.v
+// /___/ /\ Timestamp: Wed Jul 21 11:51:09 2010
+// \ \ / \
+// \___\/\___\
+//
+// Command : -w -sim -ofmt verilog /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.ngc /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.v
+// Device : xc3s2000-fg456-5
+// Input file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.ngc
+// Output file : /home/ianb/ettus/sram_fifo/fpgapriv/usrp2/extramfifo/tmp/_cg/ila.v
+// # of Modules : 1
+// Design Name : ila
+// Xilinx : /opt/Xilinx/12.1/ISE_DS/ISE
+//
+// Purpose:
+// This verilog netlist is a verification model and uses simulation
+// primitives which may not represent the true implementation of the
+// device, however the netlist is functionally correct and should not
+// be modified. This file cannot be synthesized and should only be used
+// with supported simulation tools.
+//
+// Reference:
+// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1 ns/1 ps
+
+module ila (
+ CLK, CONTROL, TRIG0, TRIG1, TRIG2, TRIG3
+)/* synthesis syn_black_box syn_noprune=1 */;
+ input CLK;
+ inout [35 : 0] CONTROL;
+ input [7 : 0] TRIG0;
+ input [7 : 0] TRIG1;
+ input [7 : 0] TRIG2;
+ input [3 : 0] TRIG3;
+
+ // synthesis translate_off
+
+ wire N0;
+ wire N1;
+ wire N38;
+ wire N39;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ;
+ wire \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ;
+ wire \U0/I_NO_D.U_ILA/U_RST/HALT_pulse ;
+ wire \U0/I_NO_D.U_ILA/U_RST/POR ;
+ wire \U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ;
+ wire \U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ;
+ wire \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/NS_load ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/TDO_next ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ;
+ wire \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ;
+ wire \U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ;
+ wire \U0/I_NO_D.U_ILA/iARM ;
+ wire \U0/I_NO_D.U_ILA/iCAPTURE ;
+ wire \U0/I_NO_D.U_ILA/iCAP_DONE ;
+ wire \U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ;
+ wire \U0/I_NO_D.U_ILA/iCAP_WR_EN ;
+ wire \U0/I_NO_D.U_ILA/iDATA_DOUT ;
+ wire \U0/I_NO_D.U_ILA/iSTAT_DOUT ;
+ wire \U0/I_NO_D.U_ILA/iTRIGGER ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4_Q15_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_STAT/U_DSR_O_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B_O_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E_Q15_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<31>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<30>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<29>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<28>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<27>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<26>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<25>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<24>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<23>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<22>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<21>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<20>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<19>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<18>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<17>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<16>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<15>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<14>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<13>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<12>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<11>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<10>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<9>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<8>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<7>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<6>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<5>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<4>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<3>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<2>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<1>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<0>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<3>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<2>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<1>_UNCONNECTED ;
+ wire \NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<0>_UNCONNECTED ;
+ wire [27 : 0] \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp ;
+ wire [13 : 1] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI ;
+ wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D ;
+ wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S ;
+ wire [13 : 0] \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR ;
+ wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA ;
+ wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO ;
+ wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA ;
+ wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO ;
+ wire [7 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA ;
+ wire [7 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO ;
+ wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO ;
+ wire [7 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA ;
+ wire [7 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO ;
+ wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO ;
+ wire [3 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA ;
+ wire [3 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next ;
+ wire [8 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S ;
+ wire [8 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData ;
+ wire [4 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data ;
+ wire [16 : 1] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT ;
+ wire [9 : 0] \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN ;
+ wire [0 : 0] \U0/I_NO_D.U_ILA/U_RST/iRESET ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/U_STAT/NS_dstat ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/STATE_dstat ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT ;
+ wire [9 : 1] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI ;
+ wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D ;
+ wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S ;
+ wire [16 : 0] \U0/I_NO_D.U_ILA/U_STAT/iSTAT ;
+ wire [9 : 0] \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT ;
+ wire [1 : 1] \U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA ;
+ wire [3 : 0] \U0/I_NO_D.U_ILA/U_TRIG/trigCondIn ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES ;
+ wire [1 : 0] \U0/I_NO_D.U_ILA/iCAP_STATE ;
+ wire [8 : 0] \U0/I_NO_D.U_ILA/iCAP_WR_ADDR ;
+ wire [27 : 0] \U0/I_NO_D.U_ILA/iDATA ;
+ wire [7 : 0] \U0/I_NO_D.U_ILA/iRESET ;
+ wire [8 : 0] \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy ;
+ wire [8 : 0] \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut ;
+ wire [27 : 0] \U0/iTRIG_IN ;
+ GND XST_GND (
+ .G(N0)
+ );
+ VCC XST_VCC (
+ .P(N1)
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_HCMP_Q (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP ),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q )
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_WCNT_LCMP_Q (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP ),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q )
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_SCNT_CMP_Q (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP ),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE0 (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1 (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iCAP_WR_EN ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [7]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_EN )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG0 (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG1 (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_OUT ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [7]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_STATE [0])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_STATE [1])
+ );
+ LUT3 #(
+ .INIT ( 8'h20 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_TRIG (
+ .I0(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .I1(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .I2(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/iTRIGGER_IN )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/I_NOLUT6.I_SRL_T2.U_SRLC16E (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [5])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [4]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCE/iCFG_DIN )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/I_NOLUT6.I_SRL_T2.U_SRLC16E (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [4])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [3]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WCE/iCFG_DIN )
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF7 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iOUT )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [0])
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/kO [1])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [0])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [1])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U2_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [5]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [4]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [2])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U3_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [7]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [6]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/jO [3])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [2])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [2]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [2])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [4]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [3]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [3])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF2_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [5]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [4]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [4])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG2_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [5]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [5])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF3_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [7]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [6]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [6])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG3_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iO [7]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DATA [7])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [1]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS0/iCFG_DIN )
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF7 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iOUT )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [0])
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/kO [1])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U0_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [0])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U1_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [1])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U2_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [5]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [4]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [2])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.U3_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [7]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [6]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/jO [3])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [2]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [2])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [4]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [3]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [3])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF2_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [5]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [4]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [4])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG2_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [5]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [5])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UF3_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [7]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [6]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [6])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_S3.UG3_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iO [7]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DATA [7])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [0]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_NS1/iCFG_DIN )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/CMP_RESET )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [0])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/jO [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [6])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [2]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [2])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iO [3]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DATA [3])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [5]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CMPRESET/iCFG_DIN )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [0])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/jO [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [3])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [2]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [2])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iO [3]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DATA [3])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [2]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCRST/iCFG_DIN )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_CE )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [0]),
+ .Q15(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4_Q15_UNCONNECTED )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DATA [1])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [9]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WHCMPCE/iCFG_DIN )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_CE )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [9])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DATA [1])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [8]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_WLCMPCE/iCFG_DIN )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_NO_OREG.U_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP_CE )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF_cs_cfglut4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [8])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG_cs_cfglut4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DATA [1])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [7]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_SCMPCE/iCFG_DIN )
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.U_MUXF6 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.U0_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [0]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [0])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.U1_MUXF5 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [2]),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP_Q ),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/jO [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [0]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [7])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG0_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [1]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UF1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [2]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [2])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.UG1_CFGLUT4 (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .A2(\U0/I_NO_D.U_ILA/iTRIGGER ),
+ .A3(\U0/I_NO_D.U_ILA/iCAPTURE ),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iO [3]),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DATA [3])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [6]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iCFG_DIN )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/I_NOLUT6.I_SRL_T2.I_YES_RPM.I_YES_OREG.OUT_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_SRLT_NE_1.U_CDONE/iOUT ),
+ .R(N0),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_DONE )
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [8]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [7]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [6]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [5]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [4]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [3]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [2]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [1]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [0]),
+ .R(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_RESET ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [8])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[8].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [8]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [8]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [8])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [8])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[7].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [7]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [7])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [7])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[6].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [6]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [6])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [6])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[5].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [5]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [5])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [5])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[4].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [4]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [4])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [4])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[3].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [3]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [3])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [3])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[2].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [2]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [2])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [2])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[1].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [1]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [1])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].GnH.U_MUXCY (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/CI [1])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/G[0].U_XORCY (
+ .CI(N1),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/S [0]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_NO_TSEQ.I_SRLT_NE_1.U_SCNT/D [0])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [8]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [7]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [6]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [5]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [4]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [3]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [2]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [1]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_FDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_CE ),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [0]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [8])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[8].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [8]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [8]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [8])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [8])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[7].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [7]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [7])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [7])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[6].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [6]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [6])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [6])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[5].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [5]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [5])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [5])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[4].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [4]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [4])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [4])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[3].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [3]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [3])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [3])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[2].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [2]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [2])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [2])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[1].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1]),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [1]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [1])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].GnH.U_MUXCY (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/CI [1])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/G[0].U_XORCY (
+ .CI(N1),
+ .LI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/S [0]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_SRLT_NE_1.U_WCNT/D [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/SCNT_CMP )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[8] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [0]),
+ .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCompData [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]),
+ .A1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]),
+ .A2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]),
+ .A3(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[0] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]),
+ .A1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]),
+ .A2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]),
+ .A3(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/cfg_data [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/sel[1] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_SCNT_CMP/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_HCMP )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[8] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [2]),
+ .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED )
+,
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]),
+ .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]),
+ .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[0] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [3])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]),
+ .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]),
+ .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/sel[1] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_HCMP/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/WCNT_LCMP )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[8] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [4]),
+ .Q(\NLW_U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH_Q_UNCONNECTED )
+,
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData0 )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [0]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ),
+ .LO(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCompData [1])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]),
+ .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]),
+ .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[0] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/cfg_data [0])
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]),
+ .A1(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]),
+ .A2(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]),
+ .A3(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/cfg_data [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/sel[1] ),
+ .Q15(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_WCNT_LCMP/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_BRK1 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [3]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [4])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/U_BRK0 (
+ .I0(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [1]),
+ .I1(CONTROL[9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [2])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [8]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [8])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [7]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [7])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [6]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [6])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [5]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [5])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [4]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [4])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [3]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [3])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [2]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [2])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [1])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR_MUX (
+ .I0(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iSCNT [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]),
+ .O(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [0])
+ );
+ SRL16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.I_SRL.U_SELX (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[9]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [16]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data [0])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [8]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [8])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [8]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [8])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [7]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [7])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[7].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [7]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [7])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [6]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [6])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[6].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [6]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [6])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [5]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [5])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [5]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [5])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [4]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [4])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[4].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [4]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [4])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [3]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [3])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[3].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [3]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [3])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [2]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [2])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[2].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [2]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [2])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [1]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [1])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[1].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [1]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [1])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_CAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [0]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [0])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[0].U_iCAP_ADDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/CAP_ADDR_next [0]),
+ .R(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR [0])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[15].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [15]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [16])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[14].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [14]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [15])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[13].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [13]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [14])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[12].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [12]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [13])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[11].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [11]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [12])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[10].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [10]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [11])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[9].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [10])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[8].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [9])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[7].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [8])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[6].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [7])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[5].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [6])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[4].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [5])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [4])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [3])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[1].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [2])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[0].U_SEL (
+ .C(CONTROL[0]),
+ .CE(CONTROL[9]),
+ .D(CONTROL[1]),
+ .Q(\U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec [1])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL2 (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL3 (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_CR (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 )
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[8].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [8]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [8])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[7].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [7]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [7])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[6].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [6]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [6])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[5].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [5]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [5])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[4].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [4]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [4])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[3].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [3]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[2].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [2]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [2])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[1].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [1]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/G_NS[0].U_NSQ (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/NS_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_NUM_SAMPLES [0]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [0])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STATE1 (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_STATE [1]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STATE0 (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load ),
+ .D(\U0/I_NO_D.U_ILA/iCAP_STATE [0]),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [0])
+ );
+ FDRS #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_ARM (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .S(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat )
+ );
+ FDRS #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_TRIGGER (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .S(\U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat )
+ );
+ FDRS #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_FULL (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .S(\U0/I_NO_D.U_ILA/iCAP_DONE ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat )
+ );
+ FDRS #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_ECR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ),
+ .R(\U0/I_NO_D.U_ILA/iARM ),
+ .S(N1),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/iARM ),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ),
+ .PRE(CONTROL[13]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 )
+ );
+ LDC #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (
+ .CLR(\U0/I_NO_D.U_ILA/iARM ),
+ .D(N1),
+ .G(CONTROL[13]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_RISING (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse ),
+ .D(N1),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/ACT_dstat )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_TDO (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/TDO_next ),
+ .Q(\U0/I_NO_D.U_ILA/iSTAT_DOUT )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_GEN_DELAY[1].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ),
+ .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [0])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly1 )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1 (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT0 (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_TFDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[5]),
+ .CLR(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR ),
+ .D(CONTROL[5]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/I_H2L.U_DOUT (
+ .C(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [1]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/ACTRESET_pulse )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/U_DOUT1 (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [1])
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/U_DOUT0 (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(CONTROL[5]),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/U_RESET_EDGE/iDOUT [0])
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 )
+ );
+ LUT4 #(
+ .INIT ( 16'h5140 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 ),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_4_450 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 ),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_452 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_12_f5_446 )
+ );
+ LUT2 #(
+ .INIT ( 4'hD ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/FULL_dstat ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_14_448 )
+ );
+ LUT3 #(
+ .INIT ( 8'h53 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/STATE_dstat [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_13_447 )
+ );
+ LUT4 #(
+ .INIT ( 16'hFBEA ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 ),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_3_449 )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_7_f6_451 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_f5_456 )
+ );
+ LUT3 #(
+ .INIT ( 8'h53 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [1]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_11_445 )
+ );
+ LUT3 #(
+ .INIT ( 8'h53 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [3]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [2]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_101_444 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_8_f5_453 )
+ );
+ LUT3 #(
+ .INIT ( 8'h53 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [5]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [4]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_10_443 )
+ );
+ LUT3 #(
+ .INIT ( 8'h53 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [7]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [6]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_9_454 )
+ );
+ MUXF7 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f6_471 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_f5_478 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [1]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_14_482 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [2]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_132_481 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_0 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f51 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [4]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_131_480 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [6]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [7]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_122_477 )
+ );
+ MUXF6 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_9_f6_484 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_f5_473 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [8]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [9]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_13_479 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [10]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [11]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_121_476 )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 ),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_10_f5_470 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [12]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [13]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_12_475 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [14]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [15]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_11_472 )
+ );
+ LUT2 #(
+ .INIT ( 4'hE ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STATCMD (
+ .I0(CONTROL[4]),
+ .I1(CONTROL[5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE )
+ );
+ INV \U0/I_NO_D.U_ILA/U_STAT/U_STATCMD_n (
+ .I(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n )
+ );
+ LUT2 #(
+ .INIT ( 4'h4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_load )
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSR (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ),
+ .O(\NLW_U0/I_NO_D.U_ILA/U_STAT/U_DSR_O_UNCONNECTED )
+ );
+ LUT4 #(
+ .INIT ( 16'h0F22 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_NSL (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly3 ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/DSTAT_en_dly2 ),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/CAP_RESET_dly1 ),
+ .I3(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/NS_load )
+ );
+ LUT4 #(
+ .INIT ( 16'h0030 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[16].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [16])
+ );
+ LUT4 #(
+ .INIT ( 16'h1030 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[15].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [15])
+ );
+ LUT4 #(
+ .INIT ( 16'h0070 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[14].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [14])
+ );
+ LUT4 #(
+ .INIT ( 16'h1020 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[13].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [13])
+ );
+ LUT4 #(
+ .INIT ( 16'h0070 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[12].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [12])
+ );
+ LUT4 #(
+ .INIT ( 16'h1010 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[11].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [11])
+ );
+ LUT4 #(
+ .INIT ( 16'h0070 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[10].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [10])
+ );
+ LUT4 #(
+ .INIT ( 16'h100F ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[9].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [9])
+ );
+ LUT4 #(
+ .INIT ( 16'hFFF0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[8].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [8])
+ );
+ LUT4 #(
+ .INIT ( 16'h0004 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[7].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [7])
+ );
+ LUT4 #(
+ .INIT ( 16'h3000 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[6].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [6])
+ );
+ LUT4 #(
+ .INIT ( 16'h001F ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[5].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [5])
+ );
+ LUT4 #(
+ .INIT ( 16'hF001 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[4].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [4])
+ );
+ LUT4 #(
+ .INIT ( 16'hB610 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[3].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [3])
+ );
+ LUT4 #(
+ .INIT ( 16'h2100 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[2].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [2])
+ );
+ LUT4 #(
+ .INIT ( 16'hC102 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[1].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [1])
+ );
+ LUT4 #(
+ .INIT ( 16'h0101 ))
+ \U0/I_NO_D.U_ILA/U_STAT/F_SSTAT[0].I_STAT.U_STAT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [0])
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_CLEAR (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly [1]),
+ .I1(CONTROL[5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR )
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_XORCY (
+ .CI(N1),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].GnH.U_MUXCY (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [0])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [1])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [1])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [2])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [2]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [2])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [3])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [3]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [3])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [4])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [4]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [4])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [5])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [5]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [5])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [6])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [6]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [6])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [7])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [7]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [7])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [8])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [8]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [9])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [8])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/CI [9]),
+ .LI(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [9]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [9])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/S [9])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[0].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [0]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[1].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [1]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[2].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [2]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[3].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [3]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[4].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [4]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[5].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [5]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[6].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [6]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[7].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [7]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[8].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [8]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/G[9].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_STAT/U_STAT_CNT/D [9]),
+ .R(\U0/I_NO_D.U_ILA/U_STAT/iSTATCMD_CE_n ),
+ .Q(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_POR (
+ .C(CLK),
+ .D(N0),
+ .PRE(N0),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/POR )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[0].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_RST/iRESET [0]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [0])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[1].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [1])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[2].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [1]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [2])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[3].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [2]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [3])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[4].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [3]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [4])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[5].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [4]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [5])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[6].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [5]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [6])
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_RST/G_RST[7].U_RST (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/iRESET [6]),
+ .S(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 ),
+ .Q(\U0/I_NO_D.U_ILA/iRESET [7])
+ );
+ LUT3 #(
+ .INIT ( 8'hEF ))
+ \U0/I_NO_D.U_ILA/U_RST/U_PRST1 (
+ .I0(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ),
+ .I1(\U0/I_NO_D.U_ILA/U_RST/POR ),
+ .I2(N1),
+ .O(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 )
+ );
+ LUT4 #(
+ .INIT ( 16'hFFFE ))
+ \U0/I_NO_D.U_ILA/U_RST/U_PRST0 (
+ .I0(N0),
+ .I1(\U0/I_NO_D.U_ILA/iCAP_DONE ),
+ .I2(N0),
+ .I3(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET1 ),
+ .O(\U0/I_NO_D.U_ILA/U_RST/PRE_RESET0 )
+ );
+ LUT2 #(
+ .INIT ( 4'h4 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_RST0 (
+ .I0(\U0/I_NO_D.U_ILA/iARM ),
+ .I1(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .O(\U0/I_NO_D.U_ILA/U_RST/iRESET [0])
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_CLEAR (
+ .I0(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] ),
+ .I1(CONTROL[13]),
+ .O(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[2].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[2] )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_GEN_DELAY[1].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/HALT_pulse )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_RFDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly[0] )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]),
+ .R(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT1 (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_DOUT0 (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDIN [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/U_TFDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[13]),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iCLR ),
+ .D(CONTROL[13]),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched )
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_CLEAR (
+ .I0(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] ),
+ .I1(CONTROL[12]),
+ .O(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[4].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/iARM ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[4] )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] ),
+ .Q(\U0/I_NO_D.U_ILA/iARM )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[2].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[2] )
+ );
+ FDE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[1].U_FD (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[1] )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE (
+ .C(CLK),
+ .CE(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly[0] )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]),
+ .R(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT )
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT1 (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [1])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_DOUT0 (
+ .C(CLK),
+ .CE(N1),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ),
+ .D(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched ),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDIN [0])
+ );
+ FDCE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_TFDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[12]),
+ .CLR(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR ),
+ .D(CONTROL[12]),
+ .Q(\U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched )
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [13]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [12]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [11]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [10]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [9]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [8]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [7]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [6]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [5]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [4]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [3]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [2]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [1]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1])
+ );
+ FDRE #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_FDRE (
+ .C(CONTROL[0]),
+ .CE(CONTROL[6]),
+ .D(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [0]),
+ .R(CONTROL[14]),
+ .Q(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [13])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[13].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [13]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [13]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [13])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [13])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[12].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [12]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [12])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [12])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[11].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [11]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [11])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [11])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[10].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [10]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [10])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [10])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[9].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [9]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [9])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [9])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[8].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [8]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [8])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [8])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[7].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [7]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [7])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [7])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[6].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [6]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [6])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [6])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[5].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [5]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [5])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [5])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[4].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [4]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [4])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [4])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[3].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [3]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [3])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [3])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[2].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [2]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [2])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].GnH.U_MUXCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [2])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[1].U_XORCY (
+ .CI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1]),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [1]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [1])
+ );
+ LUT1 #(
+ .INIT ( 2'h2 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0])
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].GnH.U_MUXCY (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]),
+ .LO(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/CI [1])
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/G[0].U_XORCY (
+ .CI(N1),
+ .LI(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/S [0]),
+ .O(\U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.I_RDADDR/U_HC/D [0])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [24]),
+ .PRE(CONTROL[23]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [25]),
+ .PRE(CONTROL[23]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [26]),
+ .PRE(CONTROL[23]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [27]),
+ .PRE(CONTROL[23]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_OREG.U_OREG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N1),
+ .CE(CONTROL[23]),
+ .CLK(CONTROL[0]),
+ .D(CONTROL[1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ),
+ .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ),
+ .CE(CONTROL[23]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ),
+ .Q15
+(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED )
+
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.I_YES_MUXH.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<4> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TWMOD8_NE0.I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<3> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [0]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [1]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [2]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [3]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [4]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [5]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [6]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [7]),
+ .PRE(CONTROL[20]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ),
+ .CE(CONTROL[20]),
+ .CLK(CONTROL[0]),
+ .D(CONTROL[1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ),
+ .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ),
+ .CE(CONTROL[20]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ),
+ .Q15
+(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED )
+
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> )
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ),
+ .LI(N0),
+ .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [8]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [9]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [10]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [11]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [12]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [13]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [14]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [15]),
+ .PRE(CONTROL[21]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ),
+ .CE(CONTROL[21]),
+ .CLK(CONTROL[0]),
+ .D(CONTROL[1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ),
+ .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ),
+ .CE(CONTROL[21]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ),
+ .Q15
+(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED )
+
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> )
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ),
+ .LI(N0),
+ .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[0].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [16]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[1].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [17]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[2].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [18]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[3].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [19]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[4].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [20]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[5].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [21]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[6].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [22]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_YES_IREG.F_TW[7].U_IREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/iTRIG_IN [23]),
+ .PRE(CONTROL[22]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_OREG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [0]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLH (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<4> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<5> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<6> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<7> ),
+ .CE(CONTROL[22]),
+ .CLK(CONTROL[0]),
+ .D(CONTROL[1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ),
+ .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<0> ),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<1> ),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<2> ),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/din_dly1<3> ),
+ .CE(CONTROL[22]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCfgData ),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ),
+ .Q15
+(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_SRLT_EQ_2.U_SRLL_Q15_UNCONNECTED )
+
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> ),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<1> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> )
+ );
+ MUXCY_L \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.U_MUXL (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/sel<0> ),
+ .LO(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<0> )
+ );
+ XORCY \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/I_TW_GTE8.F_TW[0].I_YES_RPM.I_OREG.U_XORH (
+ .CI(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<1> ),
+ .LI(N0),
+ .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_MUT_GAND.U_match/I_SRL16.U_GAND_SRL16/tmpCompData<2> )
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [0]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [0])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [1]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [1])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [2]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [2])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [3]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [3])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [4]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [4])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [5]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [5])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [6]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [6])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [7]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [7])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [8]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [8])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [9]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [9])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [10]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [10])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [11]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [11])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [12]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [12])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [13]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [13])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [14]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [14])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [15]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [15])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [16]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [16])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [17]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [17])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [18]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [18])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [19]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [19])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [20]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [20])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [21]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [21])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [22]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [22])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [23]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [23])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [24]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [24])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [25]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [25])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [26]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [26])
+ );
+ FD #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.FF (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [27]),
+ .Q(\U0/I_NO_D.U_ILA/iDATA [27])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[0].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [0]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [0])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[1].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [1]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [1])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[2].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [2]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [2])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[3].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [3]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [3])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[4].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [4]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [4])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[5].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [5]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [5])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[6].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [6]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [6])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[7].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [7]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [7])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[8].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [8]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [8])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[9].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [9]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [9])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[10].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [10]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [10])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[11].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [11]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [11])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[12].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [12]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [12])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[13].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [13]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [13])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[14].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [14]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [14])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[15].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [15]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [15])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[16].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [16]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [16])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[17].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [17]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [17])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[18].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [18]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [18])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[19].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [19]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [19])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[20].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [20]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [20])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[21].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [21]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [21])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[22].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [22]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [22])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[23].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [23]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [23])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[24].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [24]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [24])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[25].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [25]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [25])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[26].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [26]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [26])
+ );
+ SRL16 #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[27].I_SRLT_NE_0.DLY9 (
+ .A0(N1),
+ .A1(N1),
+ .A2(N1),
+ .A3(N0),
+ .CLK(CLK),
+ .D(\U0/iTRIG_IN [27]),
+ .Q(\U0/I_NO_D.U_ILA/I_DQ.U_DQQ/temp [27])
+ );
+ LUT3 #(
+ .INIT ( 8'hCA ))
+ \U0/I_NO_D.U_ILA/U_DOUT (
+ .I0(\U0/I_NO_D.U_ILA/iSTAT_DOUT ),
+ .I1(\U0/I_NO_D.U_ILA/iDATA_DOUT ),
+ .I2(CONTROL[6]),
+ .O(CONTROL[3])
+ );
+ LUT1 #(
+ .INIT ( 2'h1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B (
+ .I0(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ),
+ .O(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_B_O_UNCONNECTED )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]),
+ .CE(CONTROL[8]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ),
+ .Q15
+(\NLW_U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E_Q15_UNCONNECTED )
+
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA [1]),
+ .I1(CONTROL[8]),
+ .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN )
+ );
+ SRLC16E #(
+ .INIT ( 16'h0000 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_SRLC16E (
+ .A0(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0]),
+ .A1(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1]),
+ .A2(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2]),
+ .A3(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3]),
+ .CE(CONTROL[8]),
+ .CLK(CONTROL[0]),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN ),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ),
+ .Q15(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCFG_DATA [1])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/I_NOLUT6.I_SRL_T2.U_LUT (
+ .I0(CONTROL[1]),
+ .I1(CONTROL[8]),
+ .O(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_NMU_EQ4.U_iDOUT/iCFG_DIN )
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/U_MU/DOUT_tmp ),
+ .PRE(\U0/I_NO_D.U_ILA/iRESET [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/I_MC_NO.U_NO_MC_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[2].U_M/dout_tmp ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [2])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/U_MU/DOUT_tmp ),
+ .PRE(\U0/I_NO_D.U_ILA/iRESET [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/I_MC_NO.U_NO_MC_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[1].U_M/dout_tmp ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [1])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/DOUT_tmp ),
+ .PRE(\U0/I_NO_D.U_ILA/iRESET [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/dout_tmp ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [0])
+ );
+ FDPE #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/I_OREG.I_YES_OREG.U_OREG (
+ .C(CLK),
+ .CE(N1),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/U_MU/DOUT_tmp ),
+ .PRE(\U0/I_NO_D.U_ILA/iRESET [1]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp )
+ );
+ FDS #(
+ .INIT ( 1'b1 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/I_MC_NO.U_NO_MC_REG (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[3].U_M/dout_tmp ),
+ .S(\U0/I_NO_D.U_ILA/iRESET [2]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondIn [3])
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_CAP_DLY (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [3]),
+ .Q(\U0/I_NO_D.U_ILA/iCAPTURE )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_STORAGE_QUAL.U_STORAGE_QUAL/iTRIGGER ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [4]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/iCAPTURE )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/I_OUTREG.U_DOUT (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TCL/iDOUT ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [3]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/I_SRLT_NE_1.I_NMU_1_TO_4.U_TRIGQ (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_NEQ2.U_TC_EQUATION/iTRIGGER ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [4]),
+ .Q(\U0/I_NO_D.U_ILA/U_TRIG/trigCondOut )
+ );
+ FDR #(
+ .INIT ( 1'b0 ))
+ \U0/I_NO_D.U_ILA/U_TRIG/F_NO_TCMC.U_FDR (
+ .C(CLK),
+ .D(\U0/I_NO_D.U_ILA/U_TRIG/trigCondOut ),
+ .R(\U0/I_NO_D.U_ILA/iRESET [5]),
+ .Q(\U0/I_NO_D.U_ILA/iTRIGGER )
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ3.G_TW[3].U_TQ (
+ .C(CLK),
+ .D(TRIG3[3]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [27])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ3.G_TW[2].U_TQ (
+ .C(CLK),
+ .D(TRIG3[2]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [26])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ3.G_TW[1].U_TQ (
+ .C(CLK),
+ .D(TRIG3[1]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [25])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ3.G_TW[0].U_TQ (
+ .C(CLK),
+ .D(TRIG3[0]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [24])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[7].U_TQ (
+ .C(CLK),
+ .D(TRIG2[7]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [23])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[6].U_TQ (
+ .C(CLK),
+ .D(TRIG2[6]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [22])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[5].U_TQ (
+ .C(CLK),
+ .D(TRIG2[5]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [21])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[4].U_TQ (
+ .C(CLK),
+ .D(TRIG2[4]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [20])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[3].U_TQ (
+ .C(CLK),
+ .D(TRIG2[3]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [19])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[2].U_TQ (
+ .C(CLK),
+ .D(TRIG2[2]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [18])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[1].U_TQ (
+ .C(CLK),
+ .D(TRIG2[1]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [17])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ2.G_TW[0].U_TQ (
+ .C(CLK),
+ .D(TRIG2[0]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [16])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[7].U_TQ (
+ .C(CLK),
+ .D(TRIG1[7]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [15])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[6].U_TQ (
+ .C(CLK),
+ .D(TRIG1[6]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [14])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[5].U_TQ (
+ .C(CLK),
+ .D(TRIG1[5]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [13])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[4].U_TQ (
+ .C(CLK),
+ .D(TRIG1[4]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [12])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[3].U_TQ (
+ .C(CLK),
+ .D(TRIG1[3]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [11])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[2].U_TQ (
+ .C(CLK),
+ .D(TRIG1[2]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [10])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[1].U_TQ (
+ .C(CLK),
+ .D(TRIG1[1]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [9])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ1.G_TW[0].U_TQ (
+ .C(CLK),
+ .D(TRIG1[0]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [8])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[7].U_TQ (
+ .C(CLK),
+ .D(TRIG0[7]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [7])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[6].U_TQ (
+ .C(CLK),
+ .D(TRIG0[6]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [6])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[5].U_TQ (
+ .C(CLK),
+ .D(TRIG0[5]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [5])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[4].U_TQ (
+ .C(CLK),
+ .D(TRIG0[4]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [4])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[3].U_TQ (
+ .C(CLK),
+ .D(TRIG0[3]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [3])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[2].U_TQ (
+ .C(CLK),
+ .D(TRIG0[2]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [2])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[1].U_TQ (
+ .C(CLK),
+ .D(TRIG0[1]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [1])
+ );
+ FDP #(
+ .INIT ( 1'b1 ))
+ \U0/I_TQ0.G_TW[0].U_TQ (
+ .C(CLK),
+ .D(TRIG0[0]),
+ .PRE(N0),
+ .Q(\U0/iTRIG_IN [0])
+ );
+ LUT2 #(
+ .INIT ( 4'h8 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<0> (
+ .I0(CONTROL[10]),
+ .I1(CONTROL[11]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [0])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<0> (
+ .CI(N1),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [0]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [0])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<1> (
+ .I0(CONTROL[12]),
+ .I1(CONTROL[13]),
+ .I2(CONTROL[9]),
+ .I3(CONTROL[14]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [1])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<1> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [0]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [1]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [1])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<2> (
+ .I0(CONTROL[15]),
+ .I1(CONTROL[16]),
+ .I2(CONTROL[8]),
+ .I3(CONTROL[17]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [2])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<2> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [1]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [2]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [2])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<3> (
+ .I0(CONTROL[18]),
+ .I1(CONTROL[21]),
+ .I2(CONTROL[7]),
+ .I3(CONTROL[19]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [3])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<3> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [2]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [3]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [3])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<4> (
+ .I0(CONTROL[20]),
+ .I1(CONTROL[22]),
+ .I2(CONTROL[6]),
+ .I3(CONTROL[23]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [4])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<4> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [3]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [4]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [4])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<5> (
+ .I0(CONTROL[24]),
+ .I1(CONTROL[25]),
+ .I2(CONTROL[5]),
+ .I3(CONTROL[26]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [5])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<5> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [4]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [5]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [5])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<6> (
+ .I0(CONTROL[27]),
+ .I1(CONTROL[28]),
+ .I2(CONTROL[2]),
+ .I3(CONTROL[29]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [6])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<6> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [5]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [6]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [6])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<7> (
+ .I0(CONTROL[30]),
+ .I1(CONTROL[31]),
+ .I2(CONTROL[1]),
+ .I3(CONTROL[32]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [7])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<7> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [6]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [7]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [7])
+ );
+ LUT4 #(
+ .INIT ( 16'h8000 ))
+ \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut<8> (
+ .I0(CONTROL[33]),
+ .I1(CONTROL[34]),
+ .I2(CONTROL[4]),
+ .I3(CONTROL[35]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [8])
+ );
+ MUXCY \U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy<8> (
+ .CI(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [7]),
+ .DI(N0),
+ .S(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_lut [8]),
+ .O(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8])
+ );
+ LUT4 #(
+ .INIT ( 16'hFEFF ))
+ \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/NS_dstat [8]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<2>1_537 )
+ );
+ LUT3 #(
+ .INIT ( 8'hE4 ))
+ \U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat1 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0 ),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1 ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat )
+ );
+ LUT2 #(
+ .INIT ( 4'h2 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]),
+ .I1(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 )
+ );
+ LUT4 #(
+ .INIT ( 16'h0001 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 )
+ );
+ LUT4 #(
+ .INIT ( 16'hFFFE ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [7]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [6]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [5]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [4]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 )
+ );
+ LUT4 #(
+ .INIT ( 16'hF222 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O26_465 ),
+ .I1(\U0/U_XST_CONTROLBUS_WORKAROUND/CONTROL_XST_WORKAROUND_O_cmp_eq0000_wg_cy [8]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O15_463 ),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT [16]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 )
+ );
+ LUT4 #(
+ .INIT ( 16'hAF8D ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O129 (
+ .I0(CONTROL[4]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O2_464 ),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/TDO_mux_in<0>1 ),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 ),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/TDO_next )
+ );
+ MUXF5 \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91 (
+ .I0(N38),
+ .I1(N39),
+ .S(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .O(\U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_455 )
+ );
+ LUT3 #(
+ .INIT ( 8'h15 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_F (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat ),
+ .O(N38)
+ );
+ LUT4 #(
+ .INIT ( 16'h0145 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_DMUX/U_CS_MUX/I3.U_MUX8/Mmux_O_91_G (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [2]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/EXTCAP_READY_dstat ),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/ACT_dstat ),
+ .O(N39)
+ );
+ LUT4_L #(
+ .INIT ( 16'h3F50 ))
+ \U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/ARM_dstat ),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/TRIGGER_dstat ),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [1]),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [0]),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT<1>1_535 )
+ );
+ LUT4_L #(
+ .INIT ( 16'h3120 ))
+ \U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82 (
+ .I0(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [8]),
+ .I1(\U0/I_NO_D.U_ILA/U_STAT/iSTAT_CNT [9]),
+ .I2(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O36_466 ),
+ .I3(\U0/I_NO_D.U_ILA/U_STAT/U_SMUX/U_CS_MUX/I6.U_MUX64/Mmux_O_8_f7_483 ),
+ .LO(\U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/O82_467 )
+ );
+ RAMB16_S1_S36 #(
+ .INIT_B ( 36'h000000000 ),
+ .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .INIT_A ( 1'h0 ),
+ .SIM_COLLISION_CHECK ( "ALL" ),
+ .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
+ .SRVAL_A ( 1'h0 ),
+ .WRITE_MODE_A ( "WRITE_FIRST" ),
+ .WRITE_MODE_B ( "WRITE_FIRST" ),
+ .SRVAL_B ( 36'h000000000 ))
+ \U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i (
+ .CLKA(CONTROL[0]),
+ .CLKB(CLK),
+ .ENA(CONTROL[6]),
+ .ENB(N1),
+ .WEB(\U0/I_NO_D.U_ILA/iCAP_WR_EN ),
+ .SSRA(N0),
+ .SSRB(N0),
+ .WEA(N0),
+ .DIPB({N0, N0, N0, N0}),
+ .ADDRA({\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [13], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [12], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [11],
+\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [10], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [9], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [8],
+\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [7], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [6], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [5],
+\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [4], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [3], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [2],
+\U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [1], \U0/I_NO_D.U_ILA/U_CAPSTOR/RD_ADDR [0]}),
+ .ADDRB({\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [8], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [7], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [6], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [5]
+, \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [4], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [3], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [2], \U0/I_NO_D.U_ILA/iCAP_WR_ADDR [1],
+\U0/I_NO_D.U_ILA/iCAP_WR_ADDR [0]}),
+ .DIB({N0, N0, N0, \U0/I_NO_D.U_ILA/iDATA [27], \U0/I_NO_D.U_ILA/iDATA [26], \U0/I_NO_D.U_ILA/iDATA [25], \U0/I_NO_D.U_ILA/iDATA [24],
+\U0/I_NO_D.U_ILA/iDATA [23], \U0/I_NO_D.U_ILA/iDATA [22], \U0/I_NO_D.U_ILA/iDATA [21], \U0/I_NO_D.U_ILA/iDATA [20], \U0/I_NO_D.U_ILA/iDATA [19],
+\U0/I_NO_D.U_ILA/iDATA [18], \U0/I_NO_D.U_ILA/iDATA [17], \U0/I_NO_D.U_ILA/iDATA [16], \U0/I_NO_D.U_ILA/iDATA [15], \U0/I_NO_D.U_ILA/iDATA [14],
+\U0/I_NO_D.U_ILA/iDATA [13], \U0/I_NO_D.U_ILA/iDATA [12], \U0/I_NO_D.U_ILA/iDATA [11], \U0/I_NO_D.U_ILA/iDATA [10], \U0/I_NO_D.U_ILA/iDATA [9],
+\U0/I_NO_D.U_ILA/iDATA [8], \U0/I_NO_D.U_ILA/iDATA [7], \U0/I_NO_D.U_ILA/iDATA [6], \U0/I_NO_D.U_ILA/iDATA [5], \U0/I_NO_D.U_ILA/iDATA [4],
+\U0/I_NO_D.U_ILA/iDATA [3], \U0/I_NO_D.U_ILA/iDATA [2], \U0/I_NO_D.U_ILA/iDATA [1], \U0/I_NO_D.U_ILA/iDATA [0], \U0/I_NO_D.U_ILA/iCAP_TRIGGER_OUT }),
+ .DOA({\U0/I_NO_D.U_ILA/iDATA_DOUT }),
+ .DIA({N0}),
+ .DOB({\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<31>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<30>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<29>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<28>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<27>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<26>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<25>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<24>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<23>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<22>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<21>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<20>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<19>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<18>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<17>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<16>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<15>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<14>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<13>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<12>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<11>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<10>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<9>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<8>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<7>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<6>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<5>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<4>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<3>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<2>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<1>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOB<0>_UNCONNECTED }),
+ .DOPB({\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<3>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<2>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<1>_UNCONNECTED ,
+\NLW_U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_NO_TB.I_RT1.U_RAM/G_BRAM[0].U_BRAM/ram_rt1_s1_s32_if.ram_rt1_s1_s32_i_DOPB<0>_UNCONNECTED })
+ );
+
+// synthesis translate_on
+
+endmodule
+
+// synthesis translate_off
+
+`ifndef GLBL
+`define GLBL
+
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (weak1, weak0) GSR = GSR_int;
+ assign (weak1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+
+`endif
+
+// synthesis translate_on
diff --git a/usrp2/extramfifo/ila.xco b/usrp2/extramfifo/ila.xco
new file mode 100644
index 000000000..c8d4d2f75
--- /dev/null
+++ b/usrp2/extramfifo/ila.xco
@@ -0,0 +1,130 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.1
+# Date: Wed Jul 21 18:51:14 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = false
+SET simulationfiles = Structural
+SET speedgrade = -5
+SET verilogsim = true
+SET vhdlsim = false
+# END Project Options
+# BEGIN Select
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.03.a
+# END Select
+# BEGIN Parameters
+CSET component_name=ila
+CSET counter_width_1=Disabled
+CSET counter_width_10=Disabled
+CSET counter_width_11=Disabled
+CSET counter_width_12=Disabled
+CSET counter_width_13=Disabled
+CSET counter_width_14=Disabled
+CSET counter_width_15=Disabled
+CSET counter_width_16=Disabled
+CSET counter_width_2=Disabled
+CSET counter_width_3=Disabled
+CSET counter_width_4=Disabled
+CSET counter_width_5=Disabled
+CSET counter_width_6=Disabled
+CSET counter_width_7=Disabled
+CSET counter_width_8=Disabled
+CSET counter_width_9=Disabled
+CSET data_port_width=0
+CSET data_same_as_trigger=true
+CSET enable_storage_qualification=true
+CSET enable_trigger_output_port=false
+CSET exclude_from_data_storage_1=false
+CSET exclude_from_data_storage_10=false
+CSET exclude_from_data_storage_11=false
+CSET exclude_from_data_storage_12=false
+CSET exclude_from_data_storage_13=false
+CSET exclude_from_data_storage_14=false
+CSET exclude_from_data_storage_15=false
+CSET exclude_from_data_storage_16=false
+CSET exclude_from_data_storage_2=false
+CSET exclude_from_data_storage_3=false
+CSET exclude_from_data_storage_4=false
+CSET exclude_from_data_storage_5=false
+CSET exclude_from_data_storage_6=false
+CSET exclude_from_data_storage_7=false
+CSET exclude_from_data_storage_8=false
+CSET exclude_from_data_storage_9=false
+CSET match_type_1=basic
+CSET match_type_10=basic
+CSET match_type_11=basic
+CSET match_type_12=basic
+CSET match_type_13=basic
+CSET match_type_14=basic
+CSET match_type_15=basic
+CSET match_type_16=basic
+CSET match_type_2=basic
+CSET match_type_3=basic
+CSET match_type_4=basic
+CSET match_type_5=basic
+CSET match_type_6=basic
+CSET match_type_7=basic
+CSET match_type_8=basic
+CSET match_type_9=basic
+CSET match_units_1=1
+CSET match_units_10=1
+CSET match_units_11=1
+CSET match_units_12=1
+CSET match_units_13=1
+CSET match_units_14=1
+CSET match_units_15=1
+CSET match_units_16=1
+CSET match_units_2=1
+CSET match_units_3=1
+CSET match_units_4=1
+CSET match_units_5=1
+CSET match_units_6=1
+CSET match_units_7=1
+CSET match_units_8=1
+CSET match_units_9=1
+CSET max_sequence_levels=1
+CSET number_of_trigger_ports=4
+CSET sample_data_depth=512
+CSET sample_on=Rising
+CSET trigger_port_width_1=8
+CSET trigger_port_width_10=8
+CSET trigger_port_width_11=8
+CSET trigger_port_width_12=8
+CSET trigger_port_width_13=8
+CSET trigger_port_width_14=8
+CSET trigger_port_width_15=8
+CSET trigger_port_width_16=8
+CSET trigger_port_width_2=8
+CSET trigger_port_width_3=8
+CSET trigger_port_width_4=4
+CSET trigger_port_width_5=8
+CSET trigger_port_width_6=8
+CSET trigger_port_width_7=8
+CSET trigger_port_width_8=8
+CSET trigger_port_width_9=8
+CSET use_rpms=true
+# END Parameters
+GENERATE
+# CRC: 66151c7c
diff --git a/usrp2/extramfifo/nobl_fifo.v b/usrp2/extramfifo/nobl_fifo.v
index 1bd7439ad..7ddb517c7 100644
--- a/usrp2/extramfifo/nobl_fifo.v
+++ b/usrp2/extramfifo/nobl_fifo.v
@@ -1,3 +1,9 @@
+// Since this FIFO uses a ZBT/NoBL SRAM for its storage which is a since port
+// device it can only sustain data throughput at half the RAM clock rate.
+// Fair arbitration to ensure this occurs is included in this logic and
+// requests for transactions that can not be completed are held off by (re)using the
+// "full" and "empty" flags.
+
module nobl_fifo
#(parameter WIDTH=18,DEPTH=19)
(
@@ -17,14 +23,14 @@ module nobl_fifo
output reg space_avail,
output reg [WIDTH-1:0] read_data,
input read_strobe,
- output reg data_avail
+ output reg data_avail,
+ input upstream_full // (Connect to almost full flag upstream)
);
reg [DEPTH-1:0] capacity;
reg [DEPTH-1:0] wr_pointer;
reg [DEPTH-1:0] rd_pointer;
wire [DEPTH-1:0] address;
-
reg supress;
reg data_avail_int; // Data available with high latency from ext FIFO flag
wire [WIDTH-1:0] data_in;
@@ -38,7 +44,7 @@ module nobl_fifo
assign read = read_strobe_int && data_avail_int;
assign write = write_strobe && space_avail;
- // When a read and write collision occur, supress availability flags next cycle
+ // When a read and write collision occur, supress the availability flags next cycle
// and complete write followed by read over 2 cycles. This forces balanced arbitration
// and makes for a simple logic design.
@@ -231,9 +237,11 @@ module nobl_fifo
// Start an external FIFO read as soon as a read of the buffer reg is strobed to minimise refill latency.
// If the buffer reg or the pending buffer reg is already empty also pre-emptively start a read.
- // However there must be something in ext FIFO to read.
- // This means that there can be 2 outstanding reads to the ext FIFO active at any time helping to hide latency.
- assign read_strobe_int = (read_strobe & data_avail & ~pending_avail) || (~data_avail && ~pending_avail);
+ // However there must be something in the main external FIFO to read for this to occur!.
+ // Pay special attention to upstream devices signalling full due to the number of potential in-flight reads\ that need
+ // to be stalled and stored somewhere.
+ // This means that there can be 3 outstanding reads to the ext FIFO active at any time helping to hide latency.
+ assign read_strobe_int = (read_strobe && data_avail && ~pending_avail && ~upstream_full) || (~data_avail && ~pending_avail && ~upstream_full);
//
diff --git a/usrp2/extramfifo/nobl_if.v b/usrp2/extramfifo/nobl_if.v
index 3143ce5ba..24d463b1e 100644
--- a/usrp2/extramfifo/nobl_if.v
+++ b/usrp2/extramfifo/nobl_if.v
@@ -1,3 +1,5 @@
+// Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world.
+
module nobl_if
#(parameter WIDTH=18,DEPTH=19)
(
@@ -35,9 +37,9 @@ module nobl_if
reg [WIDTH-1:0] data_out_pipe3;
assign RAM_LDn = 0;
+ // ZBT/NoBL RAM actually manages its own output enables very well.
assign RAM_OEn = 0;
-
//
// Pipeline stage 1
//
@@ -129,8 +131,5 @@ module nobl_if
else
data_in_valid <= 1'b0;
end // always @ (posedge clk)
-
-
-
-
+
endmodule // nobl_if
diff --git a/usrp2/extramfifo/test_sram_if.v b/usrp2/extramfifo/test_sram_if.v
index 9f36b409c..0e74b49eb 100644
--- a/usrp2/extramfifo/test_sram_if.v
+++ b/usrp2/extramfifo/test_sram_if.v
@@ -1,3 +1,7 @@
+// Instantiate this block at the core level to conduct closed
+// loop testing of the AC performance of the USRP2 SRAM interface
+
+
`define WIDTH 18
`define DEPTH 19
diff --git a/usrp2/fifo/fifo_cascade.v b/usrp2/fifo/fifo_cascade.v
index fdd8449bc..ff2993ed5 100644
--- a/usrp2/fifo/fifo_cascade.v
+++ b/usrp2/fifo/fifo_cascade.v
@@ -10,11 +10,11 @@ module fifo_cascade
#(parameter WIDTH=32, SIZE=9)
(input clk, input reset, input clear,
input [WIDTH-1:0] datain,
- input src_rdy_i,
- output dst_rdy_o,
+ input src_rdy_i, // WRITE
+ output dst_rdy_o, // not FULL
output [WIDTH-1:0] dataout,
- output src_rdy_o,
- input dst_rdy_i,
+ output src_rdy_o, // not EMPTY
+ input dst_rdy_i, // READ
output [15:0] space,
output [15:0] occupied);
diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common
index d0435fa1e..754471221 100644
--- a/usrp2/top/Makefile.common
+++ b/usrp2/top/Makefile.common
@@ -31,6 +31,7 @@ synth: $(ISE_FILE)
$(ISE_HELPER) "Synthesize - XST"
bin: $(BIN_FILE)
+ $(ISE_HELPER) "Generate Programming File"
mcs: $(MCS_FILE)
diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp
index 9962887d4..99effb038 100644
--- a/usrp2/top/u2_rev3/Makefile.udp
+++ b/usrp2/top/u2_rev3/Makefile.udp
@@ -24,6 +24,8 @@ include ../../vrt/Makefile.srcs
include ../../udp/Makefile.srcs
include ../../coregen/Makefile.srcs
include ../../extram/Makefile.srcs
+include ../../extramfifo/Makefile.srcs
+
##################################################
# Project Properties
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index 798022adc..33e9dbcd9 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -119,7 +119,9 @@ module u2_core
inout [15:0] io_rx,
// External RAM
- inout [17:0] RAM_D,
+ input [17:0] RAM_D_pi,
+ output [17:0] RAM_D_po,
+ output RAM_D_poe,
output [18:0] RAM_A,
output RAM_CE1n,
output RAM_CENn,
@@ -642,11 +644,37 @@ module u2_core
wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy;
wire [31:0] debug_vtc, debug_vtd, debug_vt;
-
+
+ // FIFO cascade draws from buffer pool, feeds vita tx deframer
+/* -----\/----- EXCLUDED -----\/-----
fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
.datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i),
.dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
+ -----/\----- EXCLUDED -----/\----- */
+
+ ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.DEPTH(19))
+ ext_fifo_i1
+ (
+ .int_clk(dsp_clk),
+ .ext_clk(clk_to_mac),
+ .rst(dsp_rst),
+ .RAM_D_pi(RAM_D_pi),
+ .RAM_D_po(RAM_D_po),
+ .RAM_D_poe(RAM_D_poe),
+ .RAM_A(RAM_A),
+ .RAM_WEn(RAM_WEn),
+ .RAM_CENn(RAM_CENn),
+ .RAM_LDn(RAM_LDn),
+ .RAM_OEn(RAM_OEn),
+ .RAM_CE1n(RAM_CE1n),
+ .datain({rd1_flags,rd1_dat}),
+ .src_rdy_i(rd1_ready_o), // WRITE
+ .dst_rdy_o(rd1_ready_i), // not FULL
+ .dataout(tx_data),
+ .src_rdy_o(tx_src_rdy), // not EMPTY
+ .dst_rdy_i(tx_dst_rdy)
+ );
vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
(.clk(dsp_clk), .reset(dsp_rst), .clear(0),
@@ -720,7 +748,30 @@ module u2_core
assign RAM_CE1n = 0;
assign RAM_D[17:16] = 2'bzz;
- */
+/* -----\/----- EXCLUDED -----\/-----
+ *-/
+
+ test_sram_if test_sram_if_i1
+ (
+ // .clk(wb_clk),
+ .clk(clk_to_mac),
+ .rst(wb_rst),
+ .RAM_D_pi(RAM_D_pi),
+ .RAM_D_po(RAM_D_po),
+ .RAM_D_poe(RAM_D_poe),
+ .RAM_A(RAM_A),
+ .RAM_WEn(RAM_WEn),
+ .RAM_CENn(RAM_CENn),
+ .RAM_LDn(RAM_LDn),
+ .RAM_OEn(RAM_OEn),
+ .RAM_CE1n(RAM_CE1n),
+ .correct()
+ );
+ -----/\----- EXCLUDED -----/\----- */
+
+ //assign RAM_CLK = wb_clk;
+ assign RAM_CLK = clk_to_mac;
+
// /////////////////////////////////////////////////////////////////////////
// VITA Timing
diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf
index 6aa699d2a..82d879446 100644
--- a/usrp2/top/u2_rev3/u2_rev3.ucf
+++ b/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -74,49 +74,49 @@ NET "MDC" LOC = "V18" ;
NET "PHY_INTn" LOC = "AB13" ;
NET "PHY_RESETn" LOC = "AA19" ;
NET "PHY_CLK" LOC = "V15" ;
-NET "RAM_D[0]" LOC = "N20" ;
-NET "RAM_D[1]" LOC = "N21" ;
-NET "RAM_D[2]" LOC = "N22" ;
-NET "RAM_D[3]" LOC = "M17" ;
-NET "RAM_D[4]" LOC = "M18" ;
-NET "RAM_D[5]" LOC = "M19" ;
-NET "RAM_D[6]" LOC = "M20" ;
-NET "RAM_D[7]" LOC = "M21" ;
-NET "RAM_D[8]" LOC = "M22" ;
-NET "RAM_D[9]" LOC = "Y22" ;
-NET "RAM_D[10]" LOC = "Y21" ;
-NET "RAM_D[11]" LOC = "Y20" ;
-NET "RAM_D[12]" LOC = "Y19" ;
-NET "RAM_D[13]" LOC = "W22" ;
-NET "RAM_D[14]" LOC = "W21" ;
-NET "RAM_D[15]" LOC = "W20" ;
-NET "RAM_D[16]" LOC = "W19" ;
-NET "RAM_D[17]" LOC = "V22" ;
-NET "RAM_A[0]" LOC = "U21" ;
-NET "RAM_A[1]" LOC = "T19" ;
-NET "RAM_A[2]" LOC = "V21" ;
-NET "RAM_A[3]" LOC = "V20" ;
-NET "RAM_A[4]" LOC = "T20" ;
-NET "RAM_A[5]" LOC = "T21" ;
-NET "RAM_A[6]" LOC = "T22" ;
-NET "RAM_A[7]" LOC = "T18" ;
-NET "RAM_A[8]" LOC = "R18" ;
-NET "RAM_A[9]" LOC = "P19" ;
-NET "RAM_A[10]" LOC = "P21" ;
-NET "RAM_A[11]" LOC = "P22" ;
-NET "RAM_A[12]" LOC = "N19" ;
-NET "RAM_A[13]" LOC = "N17" ;
-NET "RAM_A[14]" LOC = "N18" ;
-NET "RAM_A[15]" LOC = "T17" ;
-NET "RAM_A[16]" LOC = "U19" ;
-NET "RAM_A[17]" LOC = "U18" ;
-NET "RAM_A[18]" LOC = "V19" ;
-NET "RAM_CE1n" LOC = "U20" ;
-NET "RAM_CENn" LOC = "P18" ;
-NET "RAM_CLK" LOC = "P17" ;
-NET "RAM_WEn" LOC = "R22" ;
-NET "RAM_OEn" LOC = "R21" ;
-NET "RAM_LDn" LOC = "R19" ;
+NET "RAM_D[0]" LOC = "N20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[1]" LOC = "N21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[2]" LOC = "N22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[3]" LOC = "M17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[4]" LOC = "M18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[5]" LOC = "M19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[6]" LOC = "M20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[7]" LOC = "M21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[8]" LOC = "M22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[9]" LOC = "Y22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[10]" LOC = "Y21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[11]" LOC = "Y20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[12]" LOC = "Y19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[13]" LOC = "W22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[14]" LOC = "W21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[15]" LOC = "W20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[16]" LOC = "W19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_D[17]" LOC = "V22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[0]" LOC = "U21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[1]" LOC = "T19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[2]" LOC = "V21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[3]" LOC = "V20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[4]" LOC = "T20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[5]" LOC = "T21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[6]" LOC = "T22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[7]" LOC = "T18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[8]" LOC = "R18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[9]" LOC = "P19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[10]" LOC = "P21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[11]" LOC = "P22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[12]" LOC = "N19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[13]" LOC = "N17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[14]" LOC = "N18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[15]" LOC = "T17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[16]" LOC = "U19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[17]" LOC = "U18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_A[18]" LOC = "V19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_CE1n" LOC = "U20" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_CENn" LOC = "P18" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_CLK" LOC = "P17" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_WEn" LOC = "R22" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_OEn" LOC = "R21" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
+NET "RAM_LDn" LOC = "R19" |IOSTANDARD = LVCMOS25 |DRIVE = 12 |SLEW = FAST ;
NET "ser_enable" LOC = "W11" ;
NET "ser_prbsen" LOC = "AA3" ;
NET "ser_loopen" LOC = "Y4" ;
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v
index 3a43e4ffe..8d9a18345 100644
--- a/usrp2/top/u2_rev3/u2_rev3.v
+++ b/usrp2/top/u2_rev3/u2_rev3.v
@@ -342,100 +342,133 @@ module u2_rev3
.S(0) // Synchronous preset input
);
*/
+
+ wire [17:0] RAM_D_pi;
+ wire [17:0] RAM_D_po;
+ wire RAM_D_poe;
+
+ genvar i;
+
+ //
+ // Instantiate IO for Bidirectional bus to SRAM
+ //
+
+ generate
+ for (i=0;i<18;i=i+1)
+ begin : gen_RAM_D_IO
+
+ IOBUF #(
+ .DRIVE(12),
+ .IOSTANDARD("LVCMOS25"),
+ .SLEW("FAST")
+ )
+ RAM_D_i (
+ .O(RAM_D_pi[i]),
+ .I(RAM_D_po[i]),
+ .IO(RAM_D[i]),
+ .T(RAM_D_poe)
+ );
+ end // block: gen_RAM_D_IO
+ endgenerate
+
+
+
u2_core #(.RAM_SIZE(32768))
- u2_core(.dsp_clk (dsp_clk),
- .wb_clk (wb_clk),
- .clock_ready (clock_ready),
- .clk_to_mac (clk_to_mac),
- .pps_in (pps_in),
- .leds (leds_int),
- .debug (debug[31:0]),
- .debug_clk (debug_clk[1:0]),
- .exp_pps_in (exp_pps_in),
- .exp_pps_out (exp_pps_out),
- .GMII_COL (GMII_COL),
- .GMII_CRS (GMII_CRS),
- .GMII_TXD (GMII_TXD_unreg[7:0]),
- .GMII_TX_EN (GMII_TX_EN_unreg),
- .GMII_TX_ER (GMII_TX_ER_unreg),
- .GMII_GTX_CLK (GMII_GTX_CLK_int),
- .GMII_TX_CLK (GMII_TX_CLK),
- .GMII_RXD (GMII_RXD[7:0]),
- .GMII_RX_CLK (GMII_RX_CLK),
- .GMII_RX_DV (GMII_RX_DV),
- .GMII_RX_ER (GMII_RX_ER),
- .MDIO (MDIO),
- .MDC (MDC),
- .PHY_INTn (PHY_INTn),
- .PHY_RESETn (PHY_RESETn),
- .ser_enable (ser_enable),
- .ser_prbsen (ser_prbsen),
- .ser_loopen (ser_loopen),
- .ser_rx_en (ser_rx_en),
- .ser_tx_clk (ser_tx_clk_int),
- .ser_t (ser_t_unreg[15:0]),
- .ser_tklsb (ser_tklsb_unreg),
- .ser_tkmsb (ser_tkmsb_unreg),
- .ser_rx_clk (ser_rx_clk_buf),
- .ser_r (ser_r_int[15:0]),
- .ser_rklsb (ser_rklsb_int),
- .ser_rkmsb (ser_rkmsb_int),
- .cpld_start (cpld_start),
- .cpld_mode (cpld_mode),
- .cpld_done (cpld_done),
- .cpld_din (cpld_din),
- .cpld_clk (cpld_clk),
- .cpld_detached (cpld_detached),
- .cpld_misc (cpld_misc),
- .cpld_init_b (cpld_init_b),
- .por (~POR),
- .config_success (config_success),
- .adc_a (adc_a_reg2),
- .adc_ovf_a (adc_ovf_a_reg2),
- .adc_on_a (adc_on_a),
- .adc_oe_a (adc_oe_a),
- .adc_b (adc_b_reg2),
- .adc_ovf_b (adc_ovf_b_reg2),
- .adc_on_b (adc_on_b),
- .adc_oe_b (adc_oe_b),
- .dac_a (dac_a_int),
- .dac_b (dac_b_int),
- .scl_pad_i (scl_pad_i),
- .scl_pad_o (scl_pad_o),
- .scl_pad_oen_o (scl_pad_oen_o),
- .sda_pad_i (sda_pad_i),
- .sda_pad_o (sda_pad_o),
- .sda_pad_oen_o (sda_pad_oen_o),
- .clk_en (clk_en[1:0]),
- .clk_sel (clk_sel[1:0]),
- .clk_func (clk_func),
- .clk_status (clk_status),
- .sclk (sclk_int),
- .mosi (mosi),
- .miso (miso),
- .sen_clk (sen_clk),
- .sen_dac (sen_dac),
- .sen_tx_db (sen_tx_db),
- .sen_tx_adc (sen_tx_adc),
- .sen_tx_dac (sen_tx_dac),
- .sen_rx_db (sen_rx_db),
- .sen_rx_adc (sen_rx_adc),
- .sen_rx_dac (sen_rx_dac),
- .io_tx (io_tx[15:0]),
- .io_rx (io_rx[15:0]),
- .RAM_D (RAM_D),
- .RAM_A (RAM_A),
- .RAM_CE1n (RAM_CE1n),
- .RAM_CENn (RAM_CENn),
- .RAM_CLK (RAM_CLK),
- .RAM_WEn (RAM_WEn),
- .RAM_OEn (RAM_OEn),
- .RAM_LDn (RAM_LDn),
- .uart_tx_o (uart_tx_o),
- .uart_rx_i (uart_rx_i),
- .uart_baud_o (),
- .sim_mode (1'b0),
- .clock_divider (2)
- );
+ u2_core(.dsp_clk (dsp_clk),
+ .wb_clk (wb_clk),
+ .clock_ready (clock_ready),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .leds (leds_int),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_in (exp_pps_in),
+ .exp_pps_out (exp_pps_out),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD_unreg[7:0]),
+ .GMII_TX_EN (GMII_TX_EN_unreg),
+ .GMII_TX_ER (GMII_TX_ER_unreg),
+ .GMII_GTX_CLK (GMII_GTX_CLK_int),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_rx_en (ser_rx_en),
+ .ser_tx_clk (ser_tx_clk_int),
+ .ser_t (ser_t_unreg[15:0]),
+ .ser_tklsb (ser_tklsb_unreg),
+ .ser_tkmsb (ser_tkmsb_unreg),
+ .ser_rx_clk (ser_rx_clk_buf),
+ .ser_r (ser_r_int[15:0]),
+ .ser_rklsb (ser_rklsb_int),
+ .ser_rkmsb (ser_rkmsb_int),
+ .cpld_start (cpld_start),
+ .cpld_mode (cpld_mode),
+ .cpld_done (cpld_done),
+ .cpld_din (cpld_din),
+ .cpld_clk (cpld_clk),
+ .cpld_detached (cpld_detached),
+ .cpld_misc (cpld_misc),
+ .cpld_init_b (cpld_init_b),
+ .por (~POR),
+ .config_success (config_success),
+ .adc_a (adc_a_reg2),
+ .adc_ovf_a (adc_ovf_a_reg2),
+ .adc_on_a (adc_on_a),
+ .adc_oe_a (adc_oe_a),
+ .adc_b (adc_b_reg2),
+ .adc_ovf_b (adc_ovf_b_reg2),
+ .adc_on_b (adc_on_b),
+ .adc_oe_b (adc_oe_b),
+ .dac_a (dac_a_int),
+ .dac_b (dac_b_int),
+ .scl_pad_i (scl_pad_i),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_i (sda_pad_i),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .sclk (sclk_int),
+ .mosi (mosi),
+ .miso (miso),
+ .sen_clk (sen_clk),
+ .sen_dac (sen_dac),
+ .sen_tx_db (sen_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sen_rx_db (sen_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .io_tx (io_tx[15:0]),
+ .io_rx (io_rx[15:0]),
+ .RAM_D_pi (RAM_D_pi),
+ .RAM_D_po (RAM_D_po),
+ .RAM_D_poe (RAM_D_poe),
+ .RAM_A (RAM_A),
+ .RAM_CE1n (RAM_CE1n),
+ .RAM_CENn (RAM_CENn),
+ .RAM_CLK (RAM_CLK),
+ .RAM_WEn (RAM_WEn),
+ .RAM_OEn (RAM_OEn),
+ .RAM_LDn (RAM_LDn),
+ .uart_tx_o (uart_tx_o),
+ .uart_rx_i (uart_rx_i),
+ .uart_baud_o (),
+ .sim_mode (1'b0),
+ .clock_divider (2)
+ );
endmodule // u2_rev2
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 21:42:06 +0000