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authorJosh Blum <josh@joshknows.com>2011-08-18 16:42:26 -0700
committerJosh Blum <josh@joshknows.com>2011-08-26 13:23:21 -0700
commitd5cbb77380d8f408469735b6ed6d4e10763d63b2 (patch)
tree312ee01ad316d495be65d6aa7b4860652732816c /usrp2/top/USRP2/u2_core.v
parentccafda72b4d1acf820be26e488bbfc530ca31c65 (diff)
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usrp2: reconnect frontend calibration, timing meets
Diffstat (limited to 'usrp2/top/USRP2/u2_core.v')
-rw-r--r--usrp2/top/USRP2/u2_core.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index d54d16cf0..7415f68e5 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -432,7 +432,7 @@ module u2_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd7, 16'd2}; //major, minor
+ localparam compat_num = {16'd7, 16'd3}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),