From d5cbb77380d8f408469735b6ed6d4e10763d63b2 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 18 Aug 2011 16:42:26 -0700 Subject: usrp2: reconnect frontend calibration, timing meets --- usrp2/top/USRP2/u2_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/top/USRP2/u2_core.v') diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index d54d16cf0..7415f68e5 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -432,7 +432,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd7, 16'd2}; //major, minor + localparam compat_num = {16'd7, 16'd3}; //major, minor wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), -- cgit v1.2.3