diff options
| -rw-r--r-- | usrp2/control_lib/bootram.v | 4 | ||||
| -rw-r--r-- | usrp2/sdr_lib/rx_frontend.v | 2 | ||||
| -rw-r--r-- | usrp2/sdr_lib/tx_frontend.v | 2 | ||||
| -rw-r--r-- | usrp2/top/N2x0/u2plus_core.v | 2 | ||||
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v | 2 |
5 files changed, 6 insertions, 6 deletions
diff --git a/usrp2/control_lib/bootram.v b/usrp2/control_lib/bootram.v index fb7bd46c8..135ebad73 100644 --- a/usrp2/control_lib/bootram.v +++ b/usrp2/control_lib/bootram.v @@ -83,7 +83,7 @@ module bootram .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock .DIA(32'hffffffff), // Port A 32-bit Data Input - .DIPA(4'd0), // Port A 4-bit parity Input + .DIPA(4'hf), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input .WEA(1'b0), // Port A 4-bit Write Enable Input @@ -93,7 +93,7 @@ module bootram .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input .CLKB(clk), // Port B 1-bit Clock .DIB(dwb_dat_i), // Port B 32-bit Data Input - .DIPB(4'd0), // Port-B 4-bit parity Input + .DIPB(4'hf), // Port-B 4-bit parity Input .ENB(ENB0), // Port B 1-bit RAM Enable Input .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v index edfbe62df..5b64737b2 100644 --- a/usrp2/sdr_lib/rx_frontend.v +++ b/usrp2/sdr_lib/rx_frontend.v @@ -1,7 +1,7 @@ module rx_frontend #(parameter BASE = 0, - parameter IQCOMP_EN = 0) + parameter IQCOMP_EN = 1) (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, diff --git a/usrp2/sdr_lib/tx_frontend.v b/usrp2/sdr_lib/tx_frontend.v index 1e7f0bf31..17a6e35e0 100644 --- a/usrp2/sdr_lib/tx_frontend.v +++ b/usrp2/sdr_lib/tx_frontend.v @@ -2,7 +2,7 @@ module tx_frontend #(parameter BASE=0, parameter WIDTH_OUT=16, - parameter IQCOMP_EN=0) + parameter IQCOMP_EN=1) (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [23:0] tx_i, input [23:0] tx_q, input run, diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v index 9906daa5f..4d612bfab 100644 --- a/usrp2/top/N2x0/u2plus_core.v +++ b/usrp2/top/N2x0/u2plus_core.v @@ -427,7 +427,7 @@ module u2plus_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd7, 16'd2}; //major, minor + localparam compat_num = {16'd7, 16'd3}; //major, minor wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index d54d16cf0..7415f68e5 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -432,7 +432,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd7, 16'd2}; //major, minor + localparam compat_num = {16'd7, 16'd3}; //major, minor wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), |