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authorDaniel Jepson <daniel.jepson@ni.com>2017-09-26 09:54:54 -0700
committerMartin Braun <martin.braun@ettus.com>2017-12-22 15:04:01 -0800
commit3b716315fea52a1c1866c60c5d101e3bfe163560 (patch)
treef7abcdab937cfe73039cfff58c5ce4fe2690cf0f /mpm/python/usrp_mpm/dboard_manager
parentfebfdf27b4f776d1791e6959587b7c0773f6cbf2 (diff)
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mpm: Update TDC sync code to make it generic for N dboards
Diffstat (limited to 'mpm/python/usrp_mpm/dboard_manager')
-rw-r--r--mpm/python/usrp_mpm/dboard_manager/eiscat.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/eiscat.py b/mpm/python/usrp_mpm/dboard_manager/eiscat.py
index 822923fbf..06b647eec 100644
--- a/mpm/python/usrp_mpm/dboard_manager/eiscat.py
+++ b/mpm/python/usrp_mpm/dboard_manager/eiscat.py
@@ -571,6 +571,9 @@ class EISCAT(DboardManagerBase):
self.ref_clock_freq,
1.9E-12, # TODO don't hardcode. This should live in the EEPROM
self.INIT_PHASE_DAC_WORD,
+ 2.496e9, # lmk_vco_freq
+ [135e-9,], # target_values
+ 0x3, # spi_addr
self.log
)
_sync_db_clock(self.clock_synchronizer)