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-rw-r--r--mpm/python/usrp_mpm/dboard_manager/eiscat.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/eiscat.py b/mpm/python/usrp_mpm/dboard_manager/eiscat.py
index 822923fbf..06b647eec 100644
--- a/mpm/python/usrp_mpm/dboard_manager/eiscat.py
+++ b/mpm/python/usrp_mpm/dboard_manager/eiscat.py
@@ -571,6 +571,9 @@ class EISCAT(DboardManagerBase):
self.ref_clock_freq,
1.9E-12, # TODO don't hardcode. This should live in the EEPROM
self.INIT_PHASE_DAC_WORD,
+ 2.496e9, # lmk_vco_freq
+ [135e-9,], # target_values
+ 0x3, # spi_addr
self.log
)
_sync_db_clock(self.clock_synchronizer)