Merge branch 'master' into next

Conflicts:
	fpga/usrp2/top/u2plus/Makefile.N200

1 files changed, 17 insertions, 2 deletions

diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
index bb6fb7e3b..1ac2b804c 100644
--- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp
+++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
@@ -287,6 +287,10 @@ public:
         if (_out_rate == rate) return;
         if (rate == 61.44e6) set_clock_settings_with_external_vcxo(rate);
         else                 set_clock_settings_with_internal_vco(rate);
+        //clock rate changed! update dboard clocks and FPGA ticks per second
+        set_rx_dboard_clock_rate(rate);
+        set_tx_dboard_clock_rate(rate);
+        _iface->poke32(UE_REG_TIME64_TPS, boost::uint32_t(get_fpga_clock_rate()));
     }
 
     double get_fpga_clock_rate(void){
@@ -302,7 +306,7 @@ public:
         _ad9522_regs.out4_cmos_configuration = (enb)?
             ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON :
             ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF;
-        this->send_reg(0x0F0);
+        this->send_reg(0x0F4);
         this->latch_regs();
     }
 
@@ -327,6 +331,7 @@ public:
 
     void set_rx_dboard_clock_rate(double rate){
         assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate");
+        _rx_clock_rate = rate;
         size_t divider = size_t(this->_chan_rate/rate);
         //set the divider registers
         set_clock_divider(divider,
@@ -339,6 +344,10 @@ public:
         this->latch_regs();
     }
 
+    double get_rx_clock_rate(void){
+        return _rx_clock_rate;
+    }
+
     /***********************************************************************
      * TX Dboard Clock Control (output 6, divider 2)
      **********************************************************************/
@@ -357,6 +366,7 @@ public:
 
     void set_tx_dboard_clock_rate(double rate){
         assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate");
+        _tx_clock_rate = rate;
         size_t divider = size_t(this->_chan_rate/rate);
         //set the divider registers
         set_clock_divider(divider,
@@ -368,7 +378,11 @@ public:
         this->send_reg(0x197);
         this->latch_regs();
     }
-    
+
+    double get_tx_clock_rate(void){
+        return _tx_clock_rate;
+    }
+
     /***********************************************************************
      * Clock reference control
      **********************************************************************/
@@ -400,6 +414,7 @@ private:
     ad9522_regs_t _ad9522_regs;
     double _out_rate; //rate at the fpga and codec
     double _chan_rate; //rate before final dividers
+    double _rx_clock_rate, _tx_clock_rate;
 
     void latch_regs(void){
         _ad9522_regs.io_update = 1;