From 71e82fb3cd960153603b48d50eae077ff0fb8ace Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Wed, 16 Mar 2011 10:34:22 -0700 Subject: E100: fix test clock output enable --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index e29fe18ce..d18ccdcb9 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -302,7 +302,7 @@ public: _ad9522_regs.out4_cmos_configuration = (enb)? ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; - this->send_reg(0x0F0); + this->send_reg(0x0F4); this->latch_regs(); } -- cgit v1.2.3 From 843886694f847bb4ddfb838ca6e43094b51edec0 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 5 Mar 2011 17:19:29 +0000 Subject: usrp-e100: disabling VCO cal check, its not right, and the warning alarms people --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 3 +++ 1 file changed, 3 insertions(+) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index aba630d88..ef6179119 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -425,6 +425,8 @@ private: this->send_reg(0x18); this->latch_regs(); //wait for calibration done: + boost::this_thread::sleep(boost::posix_time::milliseconds(50)); + /* this routine seems to not work, just sleep and return... static const boost::uint8_t addr = 0x01F; for (size_t ms10 = 0; ms10 < 100; ms10++){ boost::uint32_t reg = _iface->read_spi( @@ -436,6 +438,7 @@ private: boost::this_thread::sleep(boost::posix_time::milliseconds(10)); } std::cerr << "USRP-E100 clock control: VCO calibration timeout" << std::endl; + */ } void send_all_regs(void){ -- cgit v1.2.3 From 7a949ffd2be87c0bbf5f733e71dbe81d565f0444 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 6 Mar 2011 12:35:42 +0000 Subject: usrp-e100: reinstate the VCO calibration timeout message --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 3 --- 1 file changed, 3 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index ef6179119..aba630d88 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -425,8 +425,6 @@ private: this->send_reg(0x18); this->latch_regs(); //wait for calibration done: - boost::this_thread::sleep(boost::posix_time::milliseconds(50)); - /* this routine seems to not work, just sleep and return... static const boost::uint8_t addr = 0x01F; for (size_t ms10 = 0; ms10 < 100; ms10++){ boost::uint32_t reg = _iface->read_spi( @@ -438,7 +436,6 @@ private: boost::this_thread::sleep(boost::posix_time::milliseconds(10)); } std::cerr << "USRP-E100 clock control: VCO calibration timeout" << std::endl; - */ } void send_all_regs(void){ -- cgit v1.2.3 From a2a78451d196a7f52a3e2a3bda94f52d127313d0 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 29 Mar 2011 11:38:38 -0700 Subject: usrp-e100: set the ticks-per-second every time we change clock rate --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 1 + host/lib/usrp/usrp_e100/mboard_impl.cpp | 5 ----- 2 files changed, 1 insertion(+), 5 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index aba630d88..b0bf20b67 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -287,6 +287,7 @@ public: if (_out_rate == rate) return; if (rate == 61.44e6) set_clock_settings_with_external_vcxo(rate); else set_clock_settings_with_internal_vco(rate); + _iface->poke32(UE_REG_TIME64_TPS, boost::uint32_t(get_fpga_clock_rate())); } double get_fpga_clock_rate(void){ diff --git a/host/lib/usrp/usrp_e100/mboard_impl.cpp b/host/lib/usrp/usrp_e100/mboard_impl.cpp index cec4fd0ad..29e3c5da2 100644 --- a/host/lib/usrp/usrp_e100/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e100/mboard_impl.cpp @@ -36,11 +36,6 @@ void usrp_e100_impl::mboard_init(void){ boost::bind(&usrp_e100_impl::mboard_set, this, _1, _2) ); - //set the ticks per seconds into the vita time control - _iface->poke32(UE_REG_TIME64_TPS, - boost::uint32_t(_clock_ctrl->get_fpga_clock_rate()) - ); - //init the clock config _clock_config = clock_config_t::internal(); update_clock_config(); -- cgit v1.2.3 From ee705a42fb41bf92529a02c3087167e71d5e2630 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 7 Apr 2011 15:46:31 -0500 Subject: usrp-e100: reset dboard clocks on rate change, and dont cache in dboard iface --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 16 +++++++++++++++- host/lib/usrp/usrp_e100/clock_ctrl.hpp | 12 ++++++++++++ host/lib/usrp/usrp_e100/dboard_iface.cpp | 8 +++++--- 3 files changed, 32 insertions(+), 4 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index b0bf20b67..1ac2b804c 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -287,6 +287,9 @@ public: if (_out_rate == rate) return; if (rate == 61.44e6) set_clock_settings_with_external_vcxo(rate); else set_clock_settings_with_internal_vco(rate); + //clock rate changed! update dboard clocks and FPGA ticks per second + set_rx_dboard_clock_rate(rate); + set_tx_dboard_clock_rate(rate); _iface->poke32(UE_REG_TIME64_TPS, boost::uint32_t(get_fpga_clock_rate())); } @@ -328,6 +331,7 @@ public: void set_rx_dboard_clock_rate(double rate){ assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); + _rx_clock_rate = rate; size_t divider = size_t(this->_chan_rate/rate); //set the divider registers set_clock_divider(divider, @@ -340,6 +344,10 @@ public: this->latch_regs(); } + double get_rx_clock_rate(void){ + return _rx_clock_rate; + } + /*********************************************************************** * TX Dboard Clock Control (output 6, divider 2) **********************************************************************/ @@ -358,6 +366,7 @@ public: void set_tx_dboard_clock_rate(double rate){ assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate"); + _tx_clock_rate = rate; size_t divider = size_t(this->_chan_rate/rate); //set the divider registers set_clock_divider(divider, @@ -369,7 +378,11 @@ public: this->send_reg(0x197); this->latch_regs(); } - + + double get_tx_clock_rate(void){ + return _tx_clock_rate; + } + /*********************************************************************** * Clock reference control **********************************************************************/ @@ -401,6 +414,7 @@ private: ad9522_regs_t _ad9522_regs; double _out_rate; //rate at the fpga and codec double _chan_rate; //rate before final dividers + double _rx_clock_rate, _tx_clock_rate; void latch_regs(void){ _ad9522_regs.io_update = 1; diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/usrp_e100/clock_ctrl.hpp index 623fbc73b..507f914f3 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.hpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.hpp @@ -78,6 +78,18 @@ public: */ virtual void set_tx_dboard_clock_rate(double rate) = 0; + /*! + * Get the current rx dboard clock rate. + * \return the clock rate in Hz + */ + virtual double get_rx_clock_rate(void) = 0; + + /*! + * Get the current tx dboard clock rate. + * \return the clock rate in Hz + */ + virtual double get_tx_clock_rate(void) = 0; + /*! * Enable/disable the rx dboard clock. * \param enb true to enable diff --git a/host/lib/usrp/usrp_e100/dboard_iface.cpp b/host/lib/usrp/usrp_e100/dboard_iface.cpp index 4ee354486..61b5a1c92 100644 --- a/host/lib/usrp/usrp_e100/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e100/dboard_iface.cpp @@ -97,7 +97,6 @@ private: usrp_e100_iface::sptr _iface; usrp_e100_clock_ctrl::sptr _clock; usrp_e100_codec_ctrl::sptr _codec; - uhd::dict _clock_rates; }; /*********************************************************************** @@ -115,7 +114,6 @@ dboard_iface::sptr make_usrp_e100_dboard_iface( * Clock Rates **********************************************************************/ void usrp_e100_dboard_iface::set_clock_rate(unit_t unit, double rate){ - _clock_rates[unit] = rate; switch(unit){ case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate); case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate); @@ -131,7 +129,11 @@ std::vector usrp_e100_dboard_iface::get_clock_rates(unit_t unit){ } double usrp_e100_dboard_iface::get_clock_rate(unit_t unit){ - return _clock_rates[unit]; + switch(unit){ + case UNIT_RX: return _clock->get_rx_clock_rate(); + case UNIT_TX: return _clock->get_tx_clock_rate(); + } + UHD_THROW_INVALID_CODE_PATH(); } void usrp_e100_dboard_iface::set_clock_enabled(unit_t unit, bool enb){ -- cgit v1.2.3