Pushing the bulk of UHD-3.7.0 code.

7 files changed, 893 insertions, 0 deletions

diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg b/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg
new file mode 100644
index 000000000..f52bcc090
--- /dev/null
+++ b/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg
@@ -0,0 +1,188 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="axi_crossbar_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="11" />
+   <wvobject fp_name="/axi_crossbar_tb/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_crossbar_tb/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_crossbar_tb/set_stb" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">set_stb</obj_property>
+      <obj_property name="ObjectShortName">set_stb</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_crossbar_tb/set_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">set_addr[15:0]</obj_property>
+      <obj_property name="ObjectShortName">set_addr[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_crossbar_tb/set_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">set_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">set_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_crossbar_tb/local_addr" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">local_addr</obj_property>
+      <obj_property name="ObjectShortName">local_addr</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider67" type="divider">
+      <obj_property name="label">New Divider</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="BkColor">128 128 255</obj_property>
+      <obj_property name="TextColor">230 230 230</obj_property>
+   </wvobject>
+   <wvobject fp_name="group6" type="group">
+      <obj_property name="label">Input Port 0</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="divider64" type="divider">
+         <obj_property name="label">New Divider</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="BkColor">128 128 255</obj_property>
+         <obj_property name="TextColor">230 230 230</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group10" type="group">
+      <obj_property name="label">Input Port 1</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="divider65" type="divider">
+         <obj_property name="label">New Divider</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="BkColor">128 128 255</obj_property>
+         <obj_property name="TextColor">230 230 230</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group14" type="group">
+      <obj_property name="label">Output Port 0</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="divider66" type="divider">
+         <obj_property name="label">New Divider</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="BkColor">128 128 255</obj_property>
+         <obj_property name="TextColor">230 230 230</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group18" type="group">
+      <obj_property name="label">Output Port 1</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+   </wvobject>
+</wave_config>
diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim
new file mode 100755
index 000000000..6c3fde52c
--- /dev/null
+++ b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim
@@ -0,0 +1,15 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -i ../.. -work work ../../../lib/control/axi_crossbar_tb.v
+vlogcomp -work work ../../../lib/control/axi_crossbar.v
+vlogcomp -work work ../../../lib/control/axi_slave_mux.v
+vlogcomp -work work ../../../lib/control/axi_forwarding_cam.v
+vlogcomp -work work ../../../lib/control/setting_reg.v
+vlogcomp -work work ../../../lib/fifo/monitor_axi_fifo.v
+vlogcomp -work work ../../../lib/fifo/axi_fifo_short.v
+
+
+
+fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe
+
+# run the simulation scrip
+./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl
diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog
new file mode 100755
index 000000000..268127de8
--- /dev/null
+++ b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog
@@ -0,0 +1,21 @@
+
+iverilog \
+-s axi_crossbar_tb \
+-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims \
+-o axi_crossbar_tb \
+-I .. \
+/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/glbl.v \
+../../lib/control/axi_crossbar_tb.v \
+../../lib/control/axi_crossbar.v \
+../../lib/control/axi_slave_mux.v \
+../../lib/control/axi_forwarding_cam.v \
+../../lib/control/setting_reg.v \
+../../lib/fifo/monitor_axi_fifo.v \
+../../lib/fifo/axi_fifo_short.v
+
+
+
+#fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe
+
+# run the simulation scrip
+#./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl
diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v b/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v
new file mode 100644
index 000000000..da0213c72
--- /dev/null
+++ b/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v
@@ -0,0 +1,136 @@
+// Simulate a 2x2 switch configuration
+localparam NUM_INPUTS = 2;
+localparam NUM_OUTPUTS = 2;
+
+//initial $dumpfile("axi_crossbar_tb.vcd");
+//initial $dumpvars(0,axi_crossbar_tb);
+
+reg [15:0] x;
+reg [31:0] seq_i0, seq_i1, seq_o0, seq_o1;
+
+
+/////////////////////////////////////////////
+//
+// Control and input data thread.
+//
+/////////////////////////////////////////////
+initial
+  begin
+     @(posedge clk);
+     reset <= 1;
+     repeat (5) @(posedge clk);
+     @(posedge clk);
+     reset <= 0;
+     @(posedge clk);
+     // 2x2 Switch so only mask one bit of SID for route dest.
+     // Each slave must have a unique address, logic doesn't check for this.
+     //
+     // Network Addr 0 & 1 go to Slave 0.
+     write_setting_bus(0,0);   // 0.X goes to Port 0
+     write_setting_bus(1,0);   // 1.X goes to Port 0
+     // Local Addr = 2
+     write_setting_bus(512,2);
+     // Host Addr 0 & 2 go to Slave 0...
+     write_setting_bus(256,0); // 2.0 goes to Port 0
+     write_setting_bus(258,0); // 2.2 goes to Port 0
+     // ...Host Addr 1 & 3 go to Slave 1...
+     write_setting_bus(257,1); // 2.1 goes to Port 1
+     write_setting_bus(259,1); // 2.3 goes to Port 1
+     //
+/* -----\/----- EXCLUDED -----\/-----
+     @(posedge clk);
+     fork
+	begin
+	   // input_port,size,tsf,sid
+	   //
+	   // Master0, addr 0.0 to Slave0
+	   enqueue_vita_pkt(0,10,0,{16'h0,8'h0,8'h0});
+	   // Master0, addr 2.0 to Slave0
+	   enqueue_vita_pkt(0,11,'h12345678,{16'h0,8'h2,8'h0});
+	   // Master0, addr 2.3 to Slave1
+	   enqueue_vita_pkt(0,14,'h45678901,{16'h0,8'h2,8'h3});
+	   // Master0, addr 2.2 to Slave0
+	   enqueue_vita_pkt(0,11,'h67890123,{16'h0,8'h2,8'h2});
+	end
+	begin
+	   // Master1, addr 1.0 to Slave0
+	   enqueue_vita_pkt(1,12,'h23456789,{16'h0,8'h1,8'h0});
+	   // Master1, addr 2.1 to Slave1
+	   enqueue_vita_pkt(1,13,'h34567890,{16'h0,8'h2,8'h1});
+	   // Master1, addr 2.3 to Slave1
+	   enqueue_vita_pkt(1,14,'h56789012,{16'h0,8'h2,8'h3});
+	end
+     join
+ -----/\----- EXCLUDED -----/\----- */
+     //
+     @(posedge clk);
+     fork
+	begin
+	   // Master0 Sender Thread.
+	   //
+	   // Master0, addr 0.0 to Slave0
+	   for (seq_i0 = 0; seq_i0 < 10; seq_i0=seq_i0 + 1)
+	     enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,0,0,0,0,`SID(0,0,0,0));
+	   // Master1, addr 1.0 to Slave0
+	   for (seq_i0 = 20; seq_i0 < 30; seq_i0=seq_i0 + 1)
+	     enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,0,0,0,0,`SID(0,0,1,0));
+	end
+
+	begin
+	   // Master1 Sender Thread.
+	   //
+	   // Master1, addr 2.1 to Slave1
+	   for (seq_i1 = 10; seq_i1 < 20; seq_i1=seq_i1 + 1)
+	     enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h12345678+seq_i1*100,0,0,`SID(0,0,2,1));
+	   // Master0, addr 2.3 to Slave1
+	   for (seq_i1 = 30; seq_i1 < 40; seq_i1=seq_i1 + 1)
+	     enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h23456789+seq_i1*100,0,0,`SID(0,0,2,3));
+	end
+     join
+
+     repeat (1000) @(posedge clk);
+
+
+  end // initial begin
+
+
+   /////////////////////////////////////////////
+   //
+   // Control and input data thread.
+   //
+   /////////////////////////////////////////////
+   initial
+     begin
+	// Wait for reset to go high
+	while (reset!==1'b1)
+	  @(posedge clk);
+	// Wait for reset to go low
+	while (reset!==1'b0)
+	  @(posedge clk);
+	// Fork concurrent output checkers for each egress port.
+	fork
+	   begin
+	      // Slave0 Recevier thread.
+	      //
+	      // Master0, addr 0.0 to Slave0
+	      for (seq_o0 = 0; seq_o0 < 10; seq_o0=seq_o0 + 1)
+		dequeue_chdr_pkt_count(0,seq_o0,32+seq_o0,0,0,0,0,`SID(0,0,0,0));
+	      // Master1, addr 1.0 to Slave0
+	      for (seq_o0 = 20; seq_o0 < 30; seq_o0=seq_o0 + 1)
+		dequeue_chdr_pkt_count(0,seq_o0,32+seq_o0,0,0,0,0,`SID(0,0,1,0));
+	   end
+	   begin
+	      // Slave1 Receiver thread.
+	      //
+	      // Master1, addr 2.1 to Slave1
+	      for (seq_o1 = 10; seq_o1 < 20; seq_o1=seq_o1 + 1)
+		dequeue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h12345678+seq_o1*100,0,0,`SID(0,0,2,1));
+	      // Master0, addr 2.3 to Slave1
+	      for (seq_o1 = 30; seq_o1 < 40; seq_o1=seq_o1 + 1)
+		dequeue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h23456789+seq_o1*100,0,0,`SID(0,0,2,3));
+	   end
+	join
+
+	repeat (1000) @(posedge clk);
+	$finish;
+     end // initial begin
diff --git a/fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg b/fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg
new file mode 100644
index 000000000..229ca6958
--- /dev/null
+++ b/fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg
@@ -0,0 +1,330 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="axi_crossbar_tb" />
+            <top_module name="glbl" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="15" />
+   <wvobject fp_name="/axi_crossbar_tb/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_crossbar_tb/reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset</obj_property>
+      <obj_property name="ObjectShortName">reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_crossbar_tb/set_stb" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">set_stb</obj_property>
+      <obj_property name="ObjectShortName">set_stb</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_crossbar_tb/set_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">set_addr[15:0]</obj_property>
+      <obj_property name="ObjectShortName">set_addr[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_crossbar_tb/set_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">set_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">set_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/axi_crossbar_tb/local_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">local_addr[7:0]</obj_property>
+      <obj_property name="ObjectShortName">local_addr[7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider67" type="divider">
+      <obj_property name="label">New Divider</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="BkColor">128 128 255</obj_property>
+      <obj_property name="TextColor">230 230 230</obj_property>
+   </wvobject>
+   <wvobject fp_name="group6" type="group">
+      <obj_property name="label">Input Port 0</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[0].axi_fifo_short_in /o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="divider64" type="divider">
+         <obj_property name="label">New Divider</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="BkColor">128 128 255</obj_property>
+         <obj_property name="TextColor">230 230 230</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group10" type="group">
+      <obj_property name="label">Input Port 1</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[1].axi_fifo_short_in /o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="divider65" type="divider">
+         <obj_property name="label">New Divider</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="BkColor">128 128 255</obj_property>
+         <obj_property name="TextColor">230 230 230</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group62" type="group">
+      <obj_property name="label">Input Port 2</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[2].axi_fifo_short_in /i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[2].axi_fifo_short_in /i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[2].axi_fifo_short_in /i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[2].axi_fifo_short_in /o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[2].axi_fifo_short_in /o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[2].axi_fifo_short_in /o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="divider63" type="divider">
+         <obj_property name="label">New Divider</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="BkColor">128 128 255</obj_property>
+         <obj_property name="TextColor">230 230 230</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group70" type="group">
+      <obj_property name="label">Input Port 3</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[3].axi_fifo_short_in /i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[3].axi_fifo_short_in /i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[3].axi_fifo_short_in /i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[3].axi_fifo_short_in /o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[3].axi_fifo_short_in /o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\input_fifos[3].axi_fifo_short_in /o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="divider71" type="divider">
+         <obj_property name="label">New Divider</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="BkColor">128 128 255</obj_property>
+         <obj_property name="TextColor">230 230 230</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group14" type="group">
+      <obj_property name="label">Output Port 0</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[0].axi_fifo_short_out /o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="divider66" type="divider">
+         <obj_property name="label">New Divider</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="BkColor">128 128 255</obj_property>
+         <obj_property name="TextColor">230 230 230</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group18" type="group">
+      <obj_property name="label">Output Port 1</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[1].axi_fifo_short_out /o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="divider88" type="divider">
+         <obj_property name="label">New Divider</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="BkColor">128 128 255</obj_property>
+         <obj_property name="TextColor">230 230 230</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group78" type="group">
+      <obj_property name="label">Output Port 2</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[2].axi_fifo_short_out /i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[2].axi_fifo_short_out /i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[2].axi_fifo_short_out /i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[2].axi_fifo_short_out /o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[2].axi_fifo_short_out /o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[2].axi_fifo_short_out /o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="divider87" type="divider">
+         <obj_property name="label">New Divider</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="BkColor">128 128 255</obj_property>
+         <obj_property name="TextColor">230 230 230</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject fp_name="group85" type="group">
+      <obj_property name="label">Output Port 3</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[3].axi_fifo_short_out /i_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">i_tdata[64:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[3].axi_fifo_short_out /i_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tvalid</obj_property>
+         <obj_property name="ObjectShortName">i_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[3].axi_fifo_short_out /i_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">i_tready</obj_property>
+         <obj_property name="ObjectShortName">i_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[3].axi_fifo_short_out /o_tdata" type="array" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tdata[64:0]</obj_property>
+         <obj_property name="ObjectShortName">o_tdata[64:0]</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[3].axi_fifo_short_out /o_tvalid" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tvalid</obj_property>
+         <obj_property name="ObjectShortName">o_tvalid</obj_property>
+      </wvobject>
+      <wvobject fp_name="/axi_crossbar_tb/\output_fifos[3].axi_fifo_short_out /o_tready" type="logic" db_ref_id="1">
+         <obj_property name="ElementShortName">o_tready</obj_property>
+         <obj_property name="ObjectShortName">o_tready</obj_property>
+      </wvobject>
+      <wvobject fp_name="divider86" type="divider">
+         <obj_property name="label">New Divider</obj_property>
+         <obj_property name="DisplayName">label</obj_property>
+         <obj_property name="BkColor">128 128 255</obj_property>
+         <obj_property name="TextColor">230 230 230</obj_property>
+      </wvobject>
+   </wvobject>
+</wave_config>
diff --git a/fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim b/fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim
new file mode 100755
index 000000000..6c3fde52c
--- /dev/null
+++ b/fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim
@@ -0,0 +1,15 @@
+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -i ../.. -work work ../../../lib/control/axi_crossbar_tb.v
+vlogcomp -work work ../../../lib/control/axi_crossbar.v
+vlogcomp -work work ../../../lib/control/axi_slave_mux.v
+vlogcomp -work work ../../../lib/control/axi_forwarding_cam.v
+vlogcomp -work work ../../../lib/control/setting_reg.v
+vlogcomp -work work ../../../lib/fifo/monitor_axi_fifo.v
+vlogcomp -work work ../../../lib/fifo/axi_fifo_short.v
+
+
+
+fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe
+
+# run the simulation scrip
+./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl
diff --git a/fpga/usrp3/sim/axi_crossbar/sim_4x4/simulation_script.v b/fpga/usrp3/sim/axi_crossbar/sim_4x4/simulation_script.v
new file mode 100644
index 000000000..7bd1c1dab
--- /dev/null
+++ b/fpga/usrp3/sim/axi_crossbar/sim_4x4/simulation_script.v
@@ -0,0 +1,188 @@
+// Simulate a 4x4 switch configuration
+localparam NUM_INPUTS = 4;
+localparam NUM_OUTPUTS = 4;
+
+//initial $dumpfile("axi_crossbar_tb.vcd");
+//initial $dumpvars(0,axi_crossbar_tb);
+
+reg [15:0] x;
+reg [31:0] seq_i0, seq_i1, seq_i2, seq_i3, seq_o0, seq_o1, seq_o2, seq_o3;
+reg sync_flag0, sync_flag1;
+
+
+/////////////////////////////////////////////
+//
+// Control and input data thread.
+//
+/////////////////////////////////////////////
+initial
+  begin
+     // Flags to synchronise test bench threads
+     sync_flag0 <= 0;
+     sync_flag1 <= 0;
+
+     @(posedge clk);
+     reset <= 1;
+     repeat (5) @(posedge clk);
+     @(posedge clk);
+     reset <= 0;
+     @(posedge clk);
+     // 2x2 Switch so only mask one bit of SID for route dest.
+     // Each slave must have a unique address, logic doesn't check for this.
+     //
+     // Local Addr = 2
+     write_setting_bus(512,2);
+     // Network Addr 0 & 1 go to Slave 0.
+     write_setting_bus(0,0);   // 0.X goes to Port 0
+     write_setting_bus(1,0);   // 1.X goes to Port 0
+     // Host Addr 0 goes to Slave 0...
+     write_setting_bus(256,0); // 2.0 goes to Port 0
+     // ...Host Addr 1 goes to Slave 1...
+     write_setting_bus(257,1); // 2.1 goes to Port 1
+     // ...Host Addr 2 goes to Slave 2...
+     write_setting_bus(258,2); // 2.2 goes to Port 2
+     // ...Host Addr 3 goes to Slave 3...
+     write_setting_bus(259,3); // 2.3 goes to Port 3
+
+     //
+     @(posedge clk);
+     fork
+	begin
+	   // Master0 Sender Thread.
+	   //
+	   // addr 2.3 to Slave3
+	   for (seq_i0 = 0; seq_i0 < 10; seq_i0=seq_i0 + 1)
+	     enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,1,'h12345678+seq_i0*100,0,0,`SID(0,0,2,3));
+
+	   while (sync_flag0 !== 1'b1)
+	     @(posedge clk);
+
+	   //
+	   // addr 2.0 to Slave0
+	   for (seq_i0 = 30; seq_i0 < 40; seq_i0=seq_i0 + 1)
+	     enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,1,'h45678901+seq_i0*100,0,0,`SID(0,0,2,0));
+
+	end
+	begin
+	   // Master1 Sender Thread.
+	   //
+	   // addr 2.2 to Slave2
+	   for (seq_i1 = 10; seq_i1 < 20; seq_i1=seq_i1 + 1)
+	     enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h23456789+seq_i1*100,0,0,`SID(0,0,2,2));
+
+
+	   while (sync_flag1 !== 1'b1)
+	     @(posedge clk);
+
+	   //
+	   // addr 2.1 to Slave1
+	   for (seq_i1 = 20; seq_i1 < 30; seq_i1=seq_i1 + 1)
+	     enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h34567890+seq_i1*100,0,0,`SID(0,0,2,1));
+	end
+	begin
+	   // Master2 Sender Thread.
+	   //
+	   // addr 2.1 to Slave1
+	   for (seq_i2 = 20; seq_i2 < 30; seq_i2=seq_i2 + 1)
+	     enqueue_chdr_pkt_count(2,seq_i2,32+seq_i2,1,'h34567890+seq_i2*100,0,0,`SID(0,0,2,1));
+
+	   //
+	   // addr 2.2 to Slave2
+	   for (seq_i2 = 10; seq_i2 < 20; seq_i2=seq_i2 + 1)
+	     enqueue_chdr_pkt_count(2,seq_i2,32+seq_i2,1,'h23456789+seq_i2*100,0,0,`SID(0,0,2,2));
+	end
+	begin
+	   // Master3 Sender Thread.
+	   //
+	   // addr 2.0 to Slave0
+	   for (seq_i3 = 30; seq_i3 < 40; seq_i3=seq_i3 + 1)
+	     enqueue_chdr_pkt_count(3,seq_i3,32+seq_i3,1,'h45678901+seq_i3*100,0,0,`SID(0,0,2,0));
+
+	   //
+	   // addr 2.3 to Slave3
+	   for (seq_i3 = 0; seq_i3 < 10; seq_i3=seq_i3 + 1)
+	     enqueue_chdr_pkt_count(3,seq_i3,32+seq_i3,1,'h12345678+seq_i3*100,0,0,`SID(0,0,2,3));
+	end
+
+     join
+
+     repeat (1000) @(posedge clk);
+
+
+  end // initial begin
+
+
+   /////////////////////////////////////////////
+   //
+   // Control and input data thread.
+   //
+   /////////////////////////////////////////////
+   initial
+     begin
+	// Wait for reset to go high
+	while (reset!==1'b1)
+	  @(posedge clk);
+	// Wait for reset to go low
+	while (reset!==1'b0)
+	  @(posedge clk);
+	// Fork concurrent output checkers for each egress port.
+	fork
+	   begin
+	      // Slave0 Recevier thread.
+	      //
+	      // addr 2.0 to Slave0
+	      for (seq_o0 = 30; seq_o0 < 40; seq_o0=seq_o0 + 1)
+		dequeue_chdr_pkt_count(0,seq_o0,32+seq_o0,1,'h45678901+seq_o0*100,0,0,`SID(0,0,2,0));
+
+	      sync_flag0 <= 1'b1;
+
+	      //
+	      // addr 2.0 to Slave0
+	      for (seq_o0 = 30; seq_o0 < 40; seq_o0=seq_o0 + 1)
+		enqueue_chdr_pkt_count(0,seq_o0,32+seq_o0,1,'h45678901+seq_o0*100,0,0,`SID(0,0,2,0));
+	   end
+
+	   begin
+	      // Slave1 Recevier thread.
+	      //
+	      // addr 2.1 to Slave1
+	      for (seq_o1 = 20; seq_o1 < 30; seq_o1=seq_o1 + 1)
+		dequeue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h34567890+seq_o1*100,0,0,`SID(0,0,2,1));
+
+	      sync_flag1 <= 1'b1;
+
+	      //
+	      // addr 2.1 to Slave1
+	      for (seq_o1 = 20; seq_o1 < 30; seq_o1=seq_o1 + 1)
+		enqueue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h34567890+seq_o1*100,0,0,`SID(0,0,2,1));
+	   end
+
+	   begin
+	      // Slave2 Recevier thread.
+	      //
+	      // addr 2.2 to Slave2
+	      for (seq_o2 = 10; seq_o2 < 20; seq_o2=seq_o2 + 1)
+		dequeue_chdr_pkt_count(2,seq_o2,32+seq_o2,1,'h23456789+seq_o2*100,0,0,`SID(0,0,2,2));
+	      //
+	      // addr 2.2 to Slave2
+	      for (seq_o2 = 10; seq_o2 < 20; seq_o2=seq_o2 + 1)
+		enqueue_chdr_pkt_count(2,seq_o2,32+seq_o2,1,'h23456789+seq_o2*100,0,0,`SID(0,0,2,2));
+	   end
+
+	   begin
+	      // Slave3 Recevier thread.
+	      //
+	      // addr 2.3 to Slave3
+	      for (seq_o3 = 0; seq_o3 < 10; seq_o3=seq_o3 + 1)
+		dequeue_chdr_pkt_count(3,seq_o3,32+seq_o3,1,'h12345678+seq_o3*100,0,0,`SID(0,0,2,3));
+	      //
+	      // addr 2.3 to Slave3
+	      for (seq_o3 = 0; seq_o3 < 10; seq_o3=seq_o3 + 1)
+		enqueue_chdr_pkt_count(3,seq_o3,32+seq_o3,1,'h12345678+seq_o3*100,0,0,`SID(0,0,2,3));
+	   end
+
+	join
+
+	repeat (1000) @(posedge clk);
+	$finish;
+     end // initial begin