From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Fri, 14 Feb 2014 12:05:07 -0800 Subject: Pushing the bulk of UHD-3.7.0 code. --- fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg | 188 ++++++++++++ fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim | 15 + fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog | 21 ++ .../sim/axi_crossbar/sim_2x2/simulation_script.v | 136 +++++++++ fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg | 330 +++++++++++++++++++++ fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim | 15 + .../sim/axi_crossbar/sim_4x4/simulation_script.v | 188 ++++++++++++ 7 files changed, 893 insertions(+) create mode 100644 fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg create mode 100755 fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim create mode 100755 fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog create mode 100644 fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v create mode 100644 fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg create mode 100755 fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim create mode 100644 fpga/usrp3/sim/axi_crossbar/sim_4x4/simulation_script.v (limited to 'fpga/usrp3/sim/axi_crossbar') diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg b/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg new file mode 100644 index 000000000..f52bcc090 --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_2x2/default.wcfg @@ -0,0 +1,188 @@ + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + set_stb + set_stb + + + set_addr[15:0] + set_addr[15:0] + HEXRADIX + + + set_data[31:0] + set_data[31:0] + HEXRADIX + + + local_addr + local_addr + + + New Divider + label + 128 128 255 + 230 230 230 + + + Input Port 0 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Input Port 1 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Output Port 0 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Output Port 1 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim new file mode 100755 index 000000000..6c3fde52c --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_isim @@ -0,0 +1,15 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -i ../.. -work work ../../../lib/control/axi_crossbar_tb.v +vlogcomp -work work ../../../lib/control/axi_crossbar.v +vlogcomp -work work ../../../lib/control/axi_slave_mux.v +vlogcomp -work work ../../../lib/control/axi_forwarding_cam.v +vlogcomp -work work ../../../lib/control/setting_reg.v +vlogcomp -work work ../../../lib/fifo/monitor_axi_fifo.v +vlogcomp -work work ../../../lib/fifo/axi_fifo_short.v + + + +fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe + +# run the simulation scrip +./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog new file mode 100755 index 000000000..268127de8 --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_2x2/run_iverilog @@ -0,0 +1,21 @@ + +iverilog \ +-s axi_crossbar_tb \ +-y /opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/unisims \ +-o axi_crossbar_tb \ +-I .. \ +/opt/Xilinx/14.4/ISE_DS/ISE/verilog/src/glbl.v \ +../../lib/control/axi_crossbar_tb.v \ +../../lib/control/axi_crossbar.v \ +../../lib/control/axi_slave_mux.v \ +../../lib/control/axi_forwarding_cam.v \ +../../lib/control/setting_reg.v \ +../../lib/fifo/monitor_axi_fifo.v \ +../../lib/fifo/axi_fifo_short.v + + + +#fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe + +# run the simulation scrip +#./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v b/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v new file mode 100644 index 000000000..da0213c72 --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_2x2/simulation_script.v @@ -0,0 +1,136 @@ +// Simulate a 2x2 switch configuration +localparam NUM_INPUTS = 2; +localparam NUM_OUTPUTS = 2; + +//initial $dumpfile("axi_crossbar_tb.vcd"); +//initial $dumpvars(0,axi_crossbar_tb); + +reg [15:0] x; +reg [31:0] seq_i0, seq_i1, seq_o0, seq_o1; + + +///////////////////////////////////////////// +// +// Control and input data thread. +// +///////////////////////////////////////////// +initial + begin + @(posedge clk); + reset <= 1; + repeat (5) @(posedge clk); + @(posedge clk); + reset <= 0; + @(posedge clk); + // 2x2 Switch so only mask one bit of SID for route dest. + // Each slave must have a unique address, logic doesn't check for this. + // + // Network Addr 0 & 1 go to Slave 0. + write_setting_bus(0,0); // 0.X goes to Port 0 + write_setting_bus(1,0); // 1.X goes to Port 0 + // Local Addr = 2 + write_setting_bus(512,2); + // Host Addr 0 & 2 go to Slave 0... + write_setting_bus(256,0); // 2.0 goes to Port 0 + write_setting_bus(258,0); // 2.2 goes to Port 0 + // ...Host Addr 1 & 3 go to Slave 1... + write_setting_bus(257,1); // 2.1 goes to Port 1 + write_setting_bus(259,1); // 2.3 goes to Port 1 + // +/* -----\/----- EXCLUDED -----\/----- + @(posedge clk); + fork + begin + // input_port,size,tsf,sid + // + // Master0, addr 0.0 to Slave0 + enqueue_vita_pkt(0,10,0,{16'h0,8'h0,8'h0}); + // Master0, addr 2.0 to Slave0 + enqueue_vita_pkt(0,11,'h12345678,{16'h0,8'h2,8'h0}); + // Master0, addr 2.3 to Slave1 + enqueue_vita_pkt(0,14,'h45678901,{16'h0,8'h2,8'h3}); + // Master0, addr 2.2 to Slave0 + enqueue_vita_pkt(0,11,'h67890123,{16'h0,8'h2,8'h2}); + end + begin + // Master1, addr 1.0 to Slave0 + enqueue_vita_pkt(1,12,'h23456789,{16'h0,8'h1,8'h0}); + // Master1, addr 2.1 to Slave1 + enqueue_vita_pkt(1,13,'h34567890,{16'h0,8'h2,8'h1}); + // Master1, addr 2.3 to Slave1 + enqueue_vita_pkt(1,14,'h56789012,{16'h0,8'h2,8'h3}); + end + join + -----/\----- EXCLUDED -----/\----- */ + // + @(posedge clk); + fork + begin + // Master0 Sender Thread. + // + // Master0, addr 0.0 to Slave0 + for (seq_i0 = 0; seq_i0 < 10; seq_i0=seq_i0 + 1) + enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,0,0,0,0,`SID(0,0,0,0)); + // Master1, addr 1.0 to Slave0 + for (seq_i0 = 20; seq_i0 < 30; seq_i0=seq_i0 + 1) + enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,0,0,0,0,`SID(0,0,1,0)); + end + + begin + // Master1 Sender Thread. + // + // Master1, addr 2.1 to Slave1 + for (seq_i1 = 10; seq_i1 < 20; seq_i1=seq_i1 + 1) + enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h12345678+seq_i1*100,0,0,`SID(0,0,2,1)); + // Master0, addr 2.3 to Slave1 + for (seq_i1 = 30; seq_i1 < 40; seq_i1=seq_i1 + 1) + enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h23456789+seq_i1*100,0,0,`SID(0,0,2,3)); + end + join + + repeat (1000) @(posedge clk); + + + end // initial begin + + + ///////////////////////////////////////////// + // + // Control and input data thread. + // + ///////////////////////////////////////////// + initial + begin + // Wait for reset to go high + while (reset!==1'b1) + @(posedge clk); + // Wait for reset to go low + while (reset!==1'b0) + @(posedge clk); + // Fork concurrent output checkers for each egress port. + fork + begin + // Slave0 Recevier thread. + // + // Master0, addr 0.0 to Slave0 + for (seq_o0 = 0; seq_o0 < 10; seq_o0=seq_o0 + 1) + dequeue_chdr_pkt_count(0,seq_o0,32+seq_o0,0,0,0,0,`SID(0,0,0,0)); + // Master1, addr 1.0 to Slave0 + for (seq_o0 = 20; seq_o0 < 30; seq_o0=seq_o0 + 1) + dequeue_chdr_pkt_count(0,seq_o0,32+seq_o0,0,0,0,0,`SID(0,0,1,0)); + end + begin + // Slave1 Receiver thread. + // + // Master1, addr 2.1 to Slave1 + for (seq_o1 = 10; seq_o1 < 20; seq_o1=seq_o1 + 1) + dequeue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h12345678+seq_o1*100,0,0,`SID(0,0,2,1)); + // Master0, addr 2.3 to Slave1 + for (seq_o1 = 30; seq_o1 < 40; seq_o1=seq_o1 + 1) + dequeue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h23456789+seq_o1*100,0,0,`SID(0,0,2,3)); + end + join + + repeat (1000) @(posedge clk); + $finish; + end // initial begin diff --git a/fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg b/fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg new file mode 100644 index 000000000..229ca6958 --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_4x4/default.wcfg @@ -0,0 +1,330 @@ + + + + + + + + + + + + + + + clk + clk + + + reset + reset + + + set_stb + set_stb + + + set_addr[15:0] + set_addr[15:0] + HEXRADIX + + + set_data[31:0] + set_data[31:0] + HEXRADIX + + + local_addr[7:0] + local_addr[7:0] + + + New Divider + label + 128 128 255 + 230 230 230 + + + Input Port 0 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Input Port 1 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Input Port 2 + label + + i_tdata[64:0] + i_tdata[64:0] + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Input Port 3 + label + + i_tdata[64:0] + i_tdata[64:0] + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Output Port 0 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Output Port 1 + label + HEXRADIX + + i_tdata[64:0] + i_tdata[64:0] + HEXRADIX + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + HEXRADIX + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Output Port 2 + label + + i_tdata[64:0] + i_tdata[64:0] + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + + Output Port 3 + label + + i_tdata[64:0] + i_tdata[64:0] + + + i_tvalid + i_tvalid + + + i_tready + i_tready + + + o_tdata[64:0] + o_tdata[64:0] + + + o_tvalid + o_tvalid + + + o_tready + o_tready + + + New Divider + label + 128 128 255 + 230 230 230 + + + diff --git a/fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim b/fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim new file mode 100755 index 000000000..6c3fde52c --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_4x4/run_isim @@ -0,0 +1,15 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -i ../.. -work work ../../../lib/control/axi_crossbar_tb.v +vlogcomp -work work ../../../lib/control/axi_crossbar.v +vlogcomp -work work ../../../lib/control/axi_slave_mux.v +vlogcomp -work work ../../../lib/control/axi_forwarding_cam.v +vlogcomp -work work ../../../lib/control/setting_reg.v +vlogcomp -work work ../../../lib/fifo/monitor_axi_fifo.v +vlogcomp -work work ../../../lib/fifo/axi_fifo_short.v + + + +fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe + +# run the simulation scrip +./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl diff --git a/fpga/usrp3/sim/axi_crossbar/sim_4x4/simulation_script.v b/fpga/usrp3/sim/axi_crossbar/sim_4x4/simulation_script.v new file mode 100644 index 000000000..7bd1c1dab --- /dev/null +++ b/fpga/usrp3/sim/axi_crossbar/sim_4x4/simulation_script.v @@ -0,0 +1,188 @@ +// Simulate a 4x4 switch configuration +localparam NUM_INPUTS = 4; +localparam NUM_OUTPUTS = 4; + +//initial $dumpfile("axi_crossbar_tb.vcd"); +//initial $dumpvars(0,axi_crossbar_tb); + +reg [15:0] x; +reg [31:0] seq_i0, seq_i1, seq_i2, seq_i3, seq_o0, seq_o1, seq_o2, seq_o3; +reg sync_flag0, sync_flag1; + + +///////////////////////////////////////////// +// +// Control and input data thread. +// +///////////////////////////////////////////// +initial + begin + // Flags to synchronise test bench threads + sync_flag0 <= 0; + sync_flag1 <= 0; + + @(posedge clk); + reset <= 1; + repeat (5) @(posedge clk); + @(posedge clk); + reset <= 0; + @(posedge clk); + // 2x2 Switch so only mask one bit of SID for route dest. + // Each slave must have a unique address, logic doesn't check for this. + // + // Local Addr = 2 + write_setting_bus(512,2); + // Network Addr 0 & 1 go to Slave 0. + write_setting_bus(0,0); // 0.X goes to Port 0 + write_setting_bus(1,0); // 1.X goes to Port 0 + // Host Addr 0 goes to Slave 0... + write_setting_bus(256,0); // 2.0 goes to Port 0 + // ...Host Addr 1 goes to Slave 1... + write_setting_bus(257,1); // 2.1 goes to Port 1 + // ...Host Addr 2 goes to Slave 2... + write_setting_bus(258,2); // 2.2 goes to Port 2 + // ...Host Addr 3 goes to Slave 3... + write_setting_bus(259,3); // 2.3 goes to Port 3 + + // + @(posedge clk); + fork + begin + // Master0 Sender Thread. + // + // addr 2.3 to Slave3 + for (seq_i0 = 0; seq_i0 < 10; seq_i0=seq_i0 + 1) + enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,1,'h12345678+seq_i0*100,0,0,`SID(0,0,2,3)); + + while (sync_flag0 !== 1'b1) + @(posedge clk); + + // + // addr 2.0 to Slave0 + for (seq_i0 = 30; seq_i0 < 40; seq_i0=seq_i0 + 1) + enqueue_chdr_pkt_count(0,seq_i0,32+seq_i0,1,'h45678901+seq_i0*100,0,0,`SID(0,0,2,0)); + + end + begin + // Master1 Sender Thread. + // + // addr 2.2 to Slave2 + for (seq_i1 = 10; seq_i1 < 20; seq_i1=seq_i1 + 1) + enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h23456789+seq_i1*100,0,0,`SID(0,0,2,2)); + + + while (sync_flag1 !== 1'b1) + @(posedge clk); + + // + // addr 2.1 to Slave1 + for (seq_i1 = 20; seq_i1 < 30; seq_i1=seq_i1 + 1) + enqueue_chdr_pkt_count(1,seq_i1,32+seq_i1,1,'h34567890+seq_i1*100,0,0,`SID(0,0,2,1)); + end + begin + // Master2 Sender Thread. + // + // addr 2.1 to Slave1 + for (seq_i2 = 20; seq_i2 < 30; seq_i2=seq_i2 + 1) + enqueue_chdr_pkt_count(2,seq_i2,32+seq_i2,1,'h34567890+seq_i2*100,0,0,`SID(0,0,2,1)); + + // + // addr 2.2 to Slave2 + for (seq_i2 = 10; seq_i2 < 20; seq_i2=seq_i2 + 1) + enqueue_chdr_pkt_count(2,seq_i2,32+seq_i2,1,'h23456789+seq_i2*100,0,0,`SID(0,0,2,2)); + end + begin + // Master3 Sender Thread. + // + // addr 2.0 to Slave0 + for (seq_i3 = 30; seq_i3 < 40; seq_i3=seq_i3 + 1) + enqueue_chdr_pkt_count(3,seq_i3,32+seq_i3,1,'h45678901+seq_i3*100,0,0,`SID(0,0,2,0)); + + // + // addr 2.3 to Slave3 + for (seq_i3 = 0; seq_i3 < 10; seq_i3=seq_i3 + 1) + enqueue_chdr_pkt_count(3,seq_i3,32+seq_i3,1,'h12345678+seq_i3*100,0,0,`SID(0,0,2,3)); + end + + join + + repeat (1000) @(posedge clk); + + + end // initial begin + + + ///////////////////////////////////////////// + // + // Control and input data thread. + // + ///////////////////////////////////////////// + initial + begin + // Wait for reset to go high + while (reset!==1'b1) + @(posedge clk); + // Wait for reset to go low + while (reset!==1'b0) + @(posedge clk); + // Fork concurrent output checkers for each egress port. + fork + begin + // Slave0 Recevier thread. + // + // addr 2.0 to Slave0 + for (seq_o0 = 30; seq_o0 < 40; seq_o0=seq_o0 + 1) + dequeue_chdr_pkt_count(0,seq_o0,32+seq_o0,1,'h45678901+seq_o0*100,0,0,`SID(0,0,2,0)); + + sync_flag0 <= 1'b1; + + // + // addr 2.0 to Slave0 + for (seq_o0 = 30; seq_o0 < 40; seq_o0=seq_o0 + 1) + enqueue_chdr_pkt_count(0,seq_o0,32+seq_o0,1,'h45678901+seq_o0*100,0,0,`SID(0,0,2,0)); + end + + begin + // Slave1 Recevier thread. + // + // addr 2.1 to Slave1 + for (seq_o1 = 20; seq_o1 < 30; seq_o1=seq_o1 + 1) + dequeue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h34567890+seq_o1*100,0,0,`SID(0,0,2,1)); + + sync_flag1 <= 1'b1; + + // + // addr 2.1 to Slave1 + for (seq_o1 = 20; seq_o1 < 30; seq_o1=seq_o1 + 1) + enqueue_chdr_pkt_count(1,seq_o1,32+seq_o1,1,'h34567890+seq_o1*100,0,0,`SID(0,0,2,1)); + end + + begin + // Slave2 Recevier thread. + // + // addr 2.2 to Slave2 + for (seq_o2 = 10; seq_o2 < 20; seq_o2=seq_o2 + 1) + dequeue_chdr_pkt_count(2,seq_o2,32+seq_o2,1,'h23456789+seq_o2*100,0,0,`SID(0,0,2,2)); + // + // addr 2.2 to Slave2 + for (seq_o2 = 10; seq_o2 < 20; seq_o2=seq_o2 + 1) + enqueue_chdr_pkt_count(2,seq_o2,32+seq_o2,1,'h23456789+seq_o2*100,0,0,`SID(0,0,2,2)); + end + + begin + // Slave3 Recevier thread. + // + // addr 2.3 to Slave3 + for (seq_o3 = 0; seq_o3 < 10; seq_o3=seq_o3 + 1) + dequeue_chdr_pkt_count(3,seq_o3,32+seq_o3,1,'h12345678+seq_o3*100,0,0,`SID(0,0,2,3)); + // + // addr 2.3 to Slave3 + for (seq_o3 = 0; seq_o3 < 10; seq_o3=seq_o3 + 1) + enqueue_chdr_pkt_count(3,seq_o3,32+seq_o3,1,'h12345678+seq_o3*100,0,0,`SID(0,0,2,3)); + end + + join + + repeat (1000) @(posedge clk); + $finish; + end // initial begin -- cgit v1.2.3