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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
| commit | ff1546f8137f7f92bb250f685561b0c34cc0e053 (patch) | |
| tree | 7fa6fd05c8828df256a1b20e2935bd3ba9899e2c /fpga/usrp3/lib/sim/axi_fifo | |
| parent | 4f691d88123784c2b405816925f1a1aef69d18c1 (diff) | |
| download | uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.gz uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.bz2 uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.zip | |
Pushing the bulk of UHD-3.7.0 code.
Diffstat (limited to 'fpga/usrp3/lib/sim/axi_fifo')
| -rwxr-xr-x | fpga/usrp3/lib/sim/axi_fifo/run_sim | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/sim/axi_fifo/run_sim b/fpga/usrp3/lib/sim/axi_fifo/run_sim new file mode 100755 index 000000000..89bf95f1e --- /dev/null +++ b/fpga/usrp3/lib/sim/axi_fifo/run_sim @@ -0,0 +1,11 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../fifo/axi_fifo_tb.v +vlogcomp -work work ../../fifo/axi_fifo.v +vlogcomp -work work ../../control/ram_2port.v + + + +fuse work.axi_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_fifo_tb.exe + +# run the simulation scrip +./axi_fifo_tb.exe -gui #-tclbatch simcmds.tcl |