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-rwxr-xr-xfpga/usrp3/lib/sim/axi_fifo/run_sim11
1 files changed, 11 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/sim/axi_fifo/run_sim b/fpga/usrp3/lib/sim/axi_fifo/run_sim
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+++ b/fpga/usrp3/lib/sim/axi_fifo/run_sim
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+vlogcomp -work work ${XILINX}/verilog/src/glbl.v
+vlogcomp -work work ../../fifo/axi_fifo_tb.v
+vlogcomp -work work ../../fifo/axi_fifo.v
+vlogcomp -work work ../../control/ram_2port.v
+
+
+
+fuse work.axi_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_fifo_tb.exe
+
+# run the simulation scrip
+./axi_fifo_tb.exe -gui #-tclbatch simcmds.tcl