From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Fri, 14 Feb 2014 12:05:07 -0800 Subject: Pushing the bulk of UHD-3.7.0 code. --- fpga/usrp3/lib/sim/axi_fifo/run_sim | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100755 fpga/usrp3/lib/sim/axi_fifo/run_sim (limited to 'fpga/usrp3/lib/sim/axi_fifo') diff --git a/fpga/usrp3/lib/sim/axi_fifo/run_sim b/fpga/usrp3/lib/sim/axi_fifo/run_sim new file mode 100755 index 000000000..89bf95f1e --- /dev/null +++ b/fpga/usrp3/lib/sim/axi_fifo/run_sim @@ -0,0 +1,11 @@ +vlogcomp -work work ${XILINX}/verilog/src/glbl.v +vlogcomp -work work ../../fifo/axi_fifo_tb.v +vlogcomp -work work ../../fifo/axi_fifo.v +vlogcomp -work work ../../control/ram_2port.v + + + +fuse work.axi_fifo_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_fifo_tb.exe + +# run the simulation scrip +./axi_fifo_tb.exe -gui #-tclbatch simcmds.tcl -- cgit v1.2.3