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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2014-02-14 12:05:07 -0800 |
| commit | ff1546f8137f7f92bb250f685561b0c34cc0e053 (patch) | |
| tree | 7fa6fd05c8828df256a1b20e2935bd3ba9899e2c /fpga/usrp3/lib/sim/axi_crossbar/run_iverilog | |
| parent | 4f691d88123784c2b405816925f1a1aef69d18c1 (diff) | |
| download | uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.gz uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.tar.bz2 uhd-ff1546f8137f7f92bb250f685561b0c34cc0e053.zip | |
Pushing the bulk of UHD-3.7.0 code.
Diffstat (limited to 'fpga/usrp3/lib/sim/axi_crossbar/run_iverilog')
| -rwxr-xr-x | fpga/usrp3/lib/sim/axi_crossbar/run_iverilog | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog b/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog new file mode 100755 index 000000000..a23b4e4a9 --- /dev/null +++ b/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog @@ -0,0 +1,21 @@ + +iverilog \ +-s axi_crossbar_tb \ +-y ~/XILINX_verilog/ISE/verilog/src/unisims \ +-o axi_crossbar_tb \ +~/XILINX_verilog/ISE/verilog/src/glbl.v \ +../../control/axi_crossbar_tb.v \ +../../control/axi_crossbar.v \ +../../control/axi_slave_mux.v \ +../../control/axi_fifo_header.v \ +../../control/arb_qualify_master.v \ +../../control/setting_reg.v \ +../../fifo/monitor_axi_fifo.v \ +../../fifo/axi_fifo_short.v + + + +#fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe + +# run the simulation scrip +#./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl |