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-rwxr-xr-xfpga/usrp3/lib/sim/axi_crossbar/run_iverilog21
1 files changed, 21 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog b/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog
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index 000000000..a23b4e4a9
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+++ b/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog
@@ -0,0 +1,21 @@
+
+iverilog \
+-s axi_crossbar_tb \
+-y ~/XILINX_verilog/ISE/verilog/src/unisims \
+-o axi_crossbar_tb \
+~/XILINX_verilog/ISE/verilog/src/glbl.v \
+../../control/axi_crossbar_tb.v \
+../../control/axi_crossbar.v \
+../../control/axi_slave_mux.v \
+../../control/axi_fifo_header.v \
+../../control/arb_qualify_master.v \
+../../control/setting_reg.v \
+../../fifo/monitor_axi_fifo.v \
+../../fifo/axi_fifo_short.v
+
+
+
+#fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe
+
+# run the simulation scrip
+#./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl