From ff1546f8137f7f92bb250f685561b0c34cc0e053 Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Fri, 14 Feb 2014 12:05:07 -0800 Subject: Pushing the bulk of UHD-3.7.0 code. --- fpga/usrp3/lib/sim/axi_crossbar/run_iverilog | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100755 fpga/usrp3/lib/sim/axi_crossbar/run_iverilog (limited to 'fpga/usrp3/lib/sim/axi_crossbar/run_iverilog') diff --git a/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog b/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog new file mode 100755 index 000000000..a23b4e4a9 --- /dev/null +++ b/fpga/usrp3/lib/sim/axi_crossbar/run_iverilog @@ -0,0 +1,21 @@ + +iverilog \ +-s axi_crossbar_tb \ +-y ~/XILINX_verilog/ISE/verilog/src/unisims \ +-o axi_crossbar_tb \ +~/XILINX_verilog/ISE/verilog/src/glbl.v \ +../../control/axi_crossbar_tb.v \ +../../control/axi_crossbar.v \ +../../control/axi_slave_mux.v \ +../../control/axi_fifo_header.v \ +../../control/arb_qualify_master.v \ +../../control/setting_reg.v \ +../../fifo/monitor_axi_fifo.v \ +../../fifo/axi_fifo_short.v + + + +#fuse work.axi_crossbar_tb work.glbl -L unisims_ver -L xilinxcorelib_ver -o axi_crossbar_tb.exe + +# run the simulation scrip +#./axi_crossbar_tb.exe -gui #-tclbatch simcmds.tcl -- cgit v1.2.3