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| author | Wade Fife <wade.fife@ettus.com> | 2020-05-08 14:18:29 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-05-11 09:06:03 -0500 |
| commit | 7b7fa68880ca423ea3a47fc3dc97ba533921c9a5 (patch) | |
| tree | 72f5489e9c4e4cfd4dd62b9f2f2c012e6892fcb5 /fpga/usrp3/lib/rfnoc/core | |
| parent | 93626e2e871f431cc05ab3b6bb27e2d03f4a9be4 (diff) | |
| download | uhd-7b7fa68880ca423ea3a47fc3dc97ba533921c9a5.tar.gz uhd-7b7fa68880ca423ea3a47fc3dc97ba533921c9a5.tar.bz2 uhd-7b7fa68880ca423ea3a47fc3dc97ba533921c9a5.zip | |
fpga: Change default MTU to 10
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/core')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v b/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v index c73d7f365..71f38fd8b 100644 --- a/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v +++ b/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v @@ -44,7 +44,7 @@ module axis_pyld_ctxt_to_chdr #( parameter SYNC_CLKS = 0, parameter CONTEXT_FIFO_SIZE = 1, parameter PAYLOAD_FIFO_SIZE = 1, - parameter MTU = 9, + parameter MTU = 10, parameter CONTEXT_PREFETCH_EN = 1 )( // Clock, reset and settings |