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-rw-r--r--fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v b/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v
index c73d7f365..71f38fd8b 100644
--- a/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v
+++ b/fpga/usrp3/lib/rfnoc/core/axis_pyld_ctxt_to_chdr.v
@@ -44,7 +44,7 @@ module axis_pyld_ctxt_to_chdr #(
parameter SYNC_CLKS = 0,
parameter CONTEXT_FIFO_SIZE = 1,
parameter PAYLOAD_FIFO_SIZE = 1,
- parameter MTU = 9,
+ parameter MTU = 10,
parameter CONTEXT_PREFETCH_EN = 1
)(
// Clock, reset and settings