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| author | Josh Blum <josh@joshknows.com> | 2012-07-17 12:33:40 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-07-17 12:33:40 -0700 |
| commit | 1b677b1cc46718ed9473700e2bb88666b70808f3 (patch) | |
| tree | 9aa45721cb5f7b92f56243527cd2fc912ed3f976 /fpga/usrp2/top/E1x0/core_compile | |
| parent | f3e7f66907bf2d77258ae38a6117927a46fe41a6 (diff) | |
| parent | 9ecbfeb8ee52b6a59b8757cb259b325cebd05199 (diff) | |
| download | uhd-1b677b1cc46718ed9473700e2bb88666b70808f3.tar.gz uhd-1b677b1cc46718ed9473700e2bb88666b70808f3.tar.bz2 uhd-1b677b1cc46718ed9473700e2bb88666b70808f3.zip | |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/top/E1x0/core_compile')
| -rwxr-xr-x | fpga/usrp2/top/E1x0/core_compile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/E1x0/core_compile b/fpga/usrp2/top/E1x0/core_compile index 14e138fa3..dd88094ff 100755 --- a/fpga/usrp2/top/E1x0/core_compile +++ b/fpga/usrp2/top/E1x0/core_compile @@ -1,3 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../B100 -y $XILINX/verilog/src/unisims E100.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |