aboutsummaryrefslogtreecommitdiffstats
path: root/usrp2
Commit message (Collapse)AuthorAgeFilesLines
...
* | | fix syntax error which icarus allowed (filed a bug with them)Matt Ettus2010-02-251-7/+9
| | |
* | | loopback and testMatt Ettus2010-02-252-7/+38
| | |
* | | corrected logicMatt Ettus2010-02-251-17/+7
| | |
* | | edge sync on done signals so we only fill/empty one bufferMatt Ettus2010-02-252-2/+32
| | |
* | | Switched xilinx primitives because they order the bits funny in the other oneMatt Ettus2010-02-251-48/+79
| | |
* | | ISE chokes on the pure verilog version so we use the macroMatt Ettus2010-02-251-4/+49
| | |
* | | First cut at passing data buffers around on GPMC busMatt Ettus2010-02-256-25/+165
| | |
* | | Merge branch 'master' into u1eMatt Ettus2010-02-231-1/+1
|\| | | | | | | | | | | | | | Conflicts: .gitignore
| * | proper initialization of the ramMatt Ettus2010-02-231-1/+1
| |/
* | first cut at making a bidirectional 2 port ram for the gpmc data interfaceMatt Ettus2010-02-233-6/+63
| | | | | | | | ISE chokes on the unequal size ram
* | use our fancy new debug portsMatt Ettus2010-02-231-0/+3
| |
* | settings bus with 16 bit wishbone interface, put on the main wishbone in u1eMatt Ettus2010-02-223-3/+68
| |
* | remove the #1 delay in all the regs. They just slow down sims.Matt Ettus2010-02-224-96/+90
| |
* | Modified nsgpio.v to support 16 bit little endian bus interface.Matt Ettus2010-02-221-0/+124
| |
* | GPIOs now on the wishbone interfaceMatt Ettus2010-02-224-37/+54
| |
* | added gpio control to the wishboneMatt Ettus2010-02-182-11/+14
| |
* | Added I2C, UART, debug pins, misc wishbone stuffMatt Ettus2010-02-183-48/+187
| |
* | allow default uart clock dividerMatt Ettus2010-02-181-6/+7
| |
* | Fixed paths to help icarus find opencores and xilinx models. Added Xilinx ↵Matt Ettus2010-02-182-4/+7
| | | | | | | | global set and reset module.
* | speed up the presentation of registered wb data to the gpmcMatt Ettus2010-02-172-13/+20
| |
* | wishbone bridge now with minimal functionality. Need to checkMatt Ettus2010-02-168-11/+121
| | | | | | | | timing and handle wait states.
* | first cut at gpmc <-> wb bridge, split u1e into core, top, and tbMatt Ettus2010-02-166-34/+159
| |
* | copied over from safe_u1eMatt Ettus2010-02-164-0/+553
| |
* | block ram interface to GPMCMatt Ettus2010-02-161-2/+6
| |
* | basic read support for the GPMC, responds with 16'hBEEFMatt Ettus2010-02-161-2/+8
| |
* | reorg pin defsMatt Ettus2010-02-141-94/+102
| |
* | connect GPMC pins to debug busMatt Ettus2010-02-142-76/+94
| |
* | organized the pins in the ucf by functionMatt Ettus2010-02-091-56/+72
| |
* | builds a successful led blinkerMatt Ettus2010-02-093-2/+4
| |
* | first cut at blinking ledsMatt Ettus2010-02-094-345/+237
| |
* | skeletons that don't work yetMatt Ettus2010-02-092-0/+607
|/
* Moved usrp2 fpga files into usrp2 subdir.Josh Blum2010-01-22633-0/+1556369
generated by cgit v1.2.3 (git 2.39.1) at 2025-03-18 04:06:14 +0000